NANOSHEET BASED EXTENDED-GATE DEVICE INTEGRATION

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

METHODS RELATED TO RADIO-FREQUENCY SWITCHING DEVICES HAVING IMPROVED VOLTAGE HANDLING CAPABILITY

MOS TRANSISTOR HAVING SUBSTANTIALLY PARALLELPIPED-SHAPED INSULATING SPACERS

TRANSISTOR WITH TRENCH ISOLATED WELL FOR SEMICONDUCTOR DEVICE ASSEMBLIES

S-Contact for SOI

OPENING IN STRESS-INDUCING LINER(S) BETWEEN TRANSISTORS

STACKED MULTI-GATE DEVICE WITH LOW CONTACT VIA RESISTANCE AND METHODS FOR FORMING THE SAME

INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT DIFFERENTIATED ACCESS

3D semiconductor device and structure with metal layers and memory cells

DEVICES COMPRISING VERTICAL TRANSISTORS INCLUDING A CHANNEL REGION COMPRISING AN OXIDE SEMICONDUCTOR MATERIAL

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH SINGLE-CRYSTAL LAYERS

METHOD OF MAKING SOI DEVICE FROM BULK SILICON SUBSTRATE AND SOI DEVICE

SEMICONDUCTOR BACKSIDE ISOLATION FEATURE FOR MERGED EPITAXY

High Voltage Switching Device

PASSIVE DEVICE WITH THINNER Si LAYER

HIGH FREQUENCY HETEROJUNCTION BIPOLAR TRANSISTOR DEVICES

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY CELLS AND MULTIPLE METAL LAYERS

BACK-END-OF-LINE CMOS INVERTER WITH VERTICAL CHANNELS AND METHODS OF FORMING THE SAME

BACKSIDES SUBTRACTIVE M1 PATTERNING WITH BACKSIDE CONTACT REPAIR FOR TIGHT N2P SPACE

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

SEMICONDUCTOR STRUCTURE WITH ISOLATION FEATURE

TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR STRUCTURE

INTEGRATED CHIP WITH GOOD THERMAL DISSIPATION PERFORMANCE

HYBRID INTEGRATED CIRCUIT DIES

METHOD FOR PRODUCING AN ADVANCED SUBSTRATE FOR HYBRID INTEGRATION

SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS

SEMICONDUCTOR ON INSULATOR HAVING A SEMICONDUCTOR LAYER WITH DIFFERENT THICKNESSES

INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME

IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME

ELECTROSTATIC DISCHARGE USING BACKSIDE POWER DISTRIBUTION NETWORK

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLS

INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE AND METHOD FOR FORMING

FABRICATION METHOD OF METAL-FREE SOI WAFER

SEMICONDUCTOR DEVICE STRUCTURE WITH BACKSIDE CONTACT

INDUCTORLESS CIRCUITS FOR CURRENT-VOLTAGE CONTROL AND REGULATION IN GLASS CORE

CIRCUIT COMPONENTS WITH HIGH PERFORMANCE THIN FILM TRANSISTOR MATERIAL

BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE

QUANTUM ELECTRONIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Low Leakage Replacement Metal Gate FET

SYSTEMS AND METHODS FOR FABRICATING FINFETS WITH DIFFERENT THRESHOLD VOLTAGES

GATE PATTERNING FOR STACKED DEVICE STRUCTURE USING SELF-ASSEMBLED MONOLAYER

3D semiconductor devices and structures with metal layers

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device

Power Distribution Network

CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN

COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE STRUCTURE

STRUCTURE WITH ISOLATED WELL

STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER

SEMICONDUCTOR-ON-INSULATOR (SOI) SEMICONDUCTOR STRUCTURES INCLUDING A HIGH-K DIELECTRIC LAYER AND METHODS OF MANUFACTURING THE SAME

Radio-frequency switching devices having improved voltage handling capability

SEMICONDUCTOR DEVICE HAVING MERGED EPITAXIAL FEATURES WITH ARC-LIKE BOTTOM SURFACE AND METHOD OF MAKING THE SAME

DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE

LATERAL CAPACITORS OF SEMICONDUCTOR DEVICES

DEVICE WITH ISOLATION STRUCTURES IN ACTIVE REGIONS

METHOD OF MAKING A TRANSISTOR HAVING ASYMMETRIC THRESHOLD VOLTAGE AND BUCK CONVERTER

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS

Method for producing 3D semiconductor devices and structures with transistors and memory cells

DEVICE FOR DETECTING AN ELECTROMAGNETIC RADIATION INCLUDING A THERMAL DETECTOR OVER A READOUT SUBSTRATE AN ACTIVE ELECTRONIC ELEMENT OF WHICH IS LOCATED THE CLOSEST TO THE THERMAL DETECTOR

3D semiconductor device and structure with bonding and DRAM memory cells

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

Semiconductor wafer with devices having different top layer thicknesses

3D semiconductor memory device and structure with memory and metal layers

INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REGIONS

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING THE SAME

MOSFET TRANSISTOR

RF switch device with a sidewall spacer having a low dielectric constant

Forksheet transistors with dielectric or conductive spine

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

DEVICE WITH LATERALLY GRADED CHANNEL REGION

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

3D semiconductor devices and structures with metal layers

POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS

COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE

FORKSHEET TRANSISTOR STRUCTURES WITH GATE CUT SPINE

3D semiconductor device and structure with single-crystal layers

SET OF INTEGRATED STANDARD CELLS

Semiconductor Structures And Methods Of Forming The Same

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

MOS TRANSISTOR ON SOI STRUCTURE

MOS TRANSISTOR ON SOI STRUCTURE

SEMICONDUCTOR DEVICE AND FABRICATING THE SAME

INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

SEMICONDUCTOR DEVICE STRUCTURES ISOLATED BY POROUS SEMICONDUCTOR MATERIAL

S-contact for SOI

INTEGRATED CIRCUIT DEVICES INCLUDING A BACK SIDE POWER DISTRIBUTION NETWORK STRUCTURE AND METHODS OF FORMING THE SAME

Method for Forming SiGe Channel

Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Both Sides of a Substrate

Devices including stacked nanosheet transistors

FDSOI DEVICE INCLUDING SELF-ALIGNED DIFFUSION BREAK

EMBEDDED SOI STRUCTURE FOR LOW LEAKAGE MOS CAPACITOR

SUBSTRATES OF SEMICONDUCTOR DEVICES HAVING VARYING THICKNESSES OF SEMICONDUCTOR LAYERS

STRUCTURE INCLUDING TRANSISTOR USING BURIED INSULATOR LAYER AS GATE DIELECTRIC AND TRENCH ISOLATIONS IN SOURCE AND DRAIN

3D semiconductor device and structure with bonding

Semiconductor device comprising wiring layer over driver circuit

SEMICONDUCTOR DEVICE

DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER

METHOD FOR MANUFACTURING HIGH-VOLTAGE TRANSISTORS ON A SILICON-ON-INSULATOR TYPE BULK

Method and apparatus for flexible circuit cable attachment

Fin-based and bipolar electrostatic discharge devices

SEMICONDUCTOR DEVICE WITH POWER VIA

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

METHOD AND STRUCTURE OF FORMING SIDEWALL CONTACT FOR STACKED FET

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICES

MONOLITHIC MULTI-FETS

VIA CONNECTION TO BACKSIDE POWER DELIVERY NETWORK

BIOLOGICAL SENSING SYSTEM HAVING MICRO-ELECTRODE ARRAY

3D semiconductor devices and structures with transistors

3D semiconductor device and structure with metal layers

Transistor integration on a silicon-on-insulator substrate

METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING BURIED BIAS PAD

SEMICONDUCTOR DEVICE

VTFET WITH BURIED POWER RAILS

INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

3D semiconductor device and structure with bonding

An Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines

FIELD EFFECT TRANSISTOR WITH SHALLOW TRENCH ISOLATION FEATURES WITHIN SOURCE/DRAIN REGIONS

SEMICONDUCTOR FABRICATION PROCESS

SEMICONDUCTOR DEVICE

SLT integrated circuit capacitor structure and methods

MONOLITHIC INTEGRATION OF DIVERSE DEVICE TYPES WITH SHARED ELECTRICAL ISOLATION

SOI Structures with Carbon in Body Regions for Improved RF-SOI Switches

GATE STACK DIPOLE COMPENSATION FOR THRESHOLD VOLTAGE DEFINITION IN TRANSISTORS

STRUCTURE AND METHOD OF FORMING SPACERS ON UNFACETED RAISED SOURCE/DRAIN REGIONS

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST TWO SINGLE-CRYSTAL LAYERS

3D semiconductor device and structure with single-crystal layers

Isolation structure for separating different transistor regions on the same semiconductor die

HYBRID BIOFILM SEMICONDUCTOR INFORMATION SYSTEMS

INTEGRATED CIRCUIT STRUCTURES HAVING CONDUCTIVE STRUCTURES IN FIN ISOLATION REGIONS

SEMICONDUCTOR DEVICE

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

Carbon implantation for thicker gate silicide

Semiconductor-on-insulator (SOI) substrate and method for forming

HIGH DOSE IMPLANTATION FOR ULTRATHIN SEMICONDUCTOR-ON-INSULATOR SUBSTRATES

Method for forming integrated circuit

Isolation between vertically stacked nanosheet devices

Body tie optimization for stacked transistor amplifier

Hybrid Integrated Circuit Dies and Methods of Forming the Same

Method For Growing Multiple Layers of Source Drain Epitaxial Silicon in FDSOI Process

Photonics structures having a locally-thickened dielectric layer

Liquid crystal display device and electronic device

SEMICONDUCTOR DEVICE HAVING A TWO-DIMENSIONAL CHANNEL AND METHOD FOR FABRICATING THE SAME

Semiconductor-on-insulator (SOI) semiconductor structures including a high-k dielectric layer and methods of manufacturing the same

ADVANCED 3D DEVICE ARCHITECTURE USING NANOSHEETS WITH 2D MATERIALS FOR SPEED ENHANCEMENT

Manufacturing method of semiconductor device including field-effect transistor comprising buried oxide (BOX) film and silicon layer

VARIABLE ELECTRONIC ELEMENT AND CIRCUIT DEVICE

SILICON-ON-INSULATOR SUBSTRATE PROCESSING FOR TRANSISTOR ENHANCEMENT

Silicon on insulator semiconductor device with mixed doped regions

Semiconductor Device and Method for Power MOSFET on Partial SOI

CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIPLE STACKED DEVICES STRUCTURES

TRANSISTOR STACKING BY WAFER BONDING

Bulk Nanosheet with Dielectric Isolation

INTEGRATED GROUP III-NITROGEN AND SILICON TRANSISTORS ON THE SAME DIE

Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain

PROTECTION RING, METHOD FOR FORMING PROTECTION RING, AND SEMICONDUCTOR STRUCTURE

3D semiconductor devices and structures

Semiconductor structure with a second isolation dam and manufacturing method thereof

Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

METHOD FOR MANUFACTURING A SeOI INTEGRATED CIRCUIT CHIP

Multilevel semiconductor device and structure with oxide bonding

3D semiconductor device and structure with bonding

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES

CHIP PACKAGING STRUCTURE, METHOD FOR MAKING THE SAME, AND WIRELESS IDENTIFICATION TAG THEREWITH

Semiconductor structure

Varactor integrated with complementary metal-oxide semiconductor devices

Stacked field-effect transistors with a shielded output

Method for manufacturing semiconductor structure with isolation feature

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Gate stack dipole compensation for threshold voltage definition in transistors

3D semiconductor device and structure with single-crystal layers

Stacked nanosheet gate-all-around device structures

DEVICE COMPRISING SPACERS INCLUDING A LOCALISED AIRGAP AND ASSOCIATED MANUFACTURING METHODS

Semiconductor structure with shared well

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY

Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices

SOI active transfer board for three-dimensional packaging and preparation method thereof

Cross field effect transistor (XFET) library architecture power routing

Cross field effect transistor library cell architecture design

Backside electrical contacts to buried power rails

GALLIUM NITRIDE (GAN) LAYER TRANSFER FOR INTEGRATED CIRCUIT TECHNOLOGY

CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION METAL

RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS

Dual strained semiconductor substrate and patterning

VTFET with buried power rails

CMOS COMPATIBLE BIOFET

SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A BURIED HIGH RESISTIVITY LAYER

Thermal extraction of single layer transfer integrated circuits

Stacked complementary field effect transistors

S-contact for SOI

Bulk substrates with a self-aligned buried polycrystalline layer

Method for producing an advanced substrate for hybrid integration

Monolithic integration of diverse device types with shared electrical isolation

Method to produce 3D semiconductor devices and structures with memory

Nanosheet IC device with single diffusion break

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Semiconductor memory having both volatile and non-volatile functionality and method of operating

RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Display device and method of manufacturing the same

STRAINED NANOSHEETS ON SILICON-ON-INSULATOR SUBSTRATE

Integrated circuit with continuous active region and raised source/drain region

SUBSTRATE AND METHOD FOR MONOLITHIC INTEGRATION OF ELECTRONIC AND OPTOELECTRONIC DEVICES

ELECTRONIC DIE MANUFACTURING METHOD

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

3D semiconductor memory device and structure

Semiconductor on insulator having a semiconductor layer with different thicknesses

Semiconductor structure and forming method thereof

Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors

Breakdown voltage capability of high voltage device

Semiconductor device structure and methods of forming the same

Integrated chip with good thermal dissipation performance

Integrated circuit device and method for forming the same

TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR STRUCTURE

Structure and formation method of semiconductor device with backside contact

Semiconductor structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRIC SPACER FILL

Field effect transistor with shallow trench isolation features within source/drain regions

Power distribution network

Lateral bipolar junction transistor and method

3D semiconductor device and structure with memory

Diffusion barrier layer for source and drain structures to increase transistor performance

Devices including stacked nanosheet transistors

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Three-dimensional memory device

Method to produce 3D semiconductor devices and structures with memory

Semiconductor devices

METHOD OF FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE

3D semiconductor device and structure with single-crystal layers

Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes

3D semiconductor devices and structures with metal layers

Semiconductor device

Systems and methods for fabricating FinFETs with different threshold voltages

Semiconductor wafer with devices having different top layer thicknesses

Structures for radiofrequency applications and related methods

Method of making semiconductor device having buried bias pad

Fin-based and bipolar electrostatic discharge devices

3D semiconductor memory device and structure

FRONT END INTEGRATED CIRCUITS INCORPORATING DIFFERING SILICON-ON-INSULATOR TECHNOLOGIES

Method to produce 3D semiconductor devices and structures with memory

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH LOGIC GATES

Tiled lateral thyristor

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC

RF switch device with a sidewall spacer having a low dielectric constant

Semiconductor devices having multi-channel active regions and methods of forming same

Breakdown voltage capability of high voltage device

METHOD FOR PRODUCING 3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH A SINGLE-CRYSTAL LAYER

3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH A SINGLE-CRYSTAL LAYER

Semiconductor memory device

Semiconductor-on-insulator (SOI) substrate and method for forming

VARIOUS 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS

Set of integrated standard cells

DIPOLE THRESHOLD VOLTAGE TUNING FOR HIGH VOLTAGE TRANSISTOR STACKS

Array of capacitors, an array of memory cells, method used in forming an array of memory cells, methods used in forming an array of capacitors, and methods used in forming a plurality of horizontally-spaced conductive lines

Methods of forming transistors and methods of forming devices comprising transistors

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES

3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

Array of capacitors, an array of memory cells, method used in forming an array of memory cells, methods used in forming an array of capacitors, and methods used in forming a plurality of horizontally-spaced conductive lines

UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES

Methods for preparing a SOI structure

METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE

Semiconductor device

Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors with defect prevention structures

Integrated circuit with active region jogs

Monolithic multi-FETS

Systems and methods for manufacturing flexible electronics

Fabrication method of metal-free SOI wafer

3D semiconductor device and structure with transistors

Semiconductor device

Power distribution network

3D semiconductor devices and structures with at least two single-crystal layers

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Epitaxial single crystalline silicon growth for memory arrays

Semiconductor structure and manufacturing method thereof

Connections from buried interconnects to device terminals in multiple stacked devices structures

Method and apparatus for flexible circuit cable attachment

Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer

Forksheet transistors with dielectric or conductive spine

3D semiconductor memory device and structure

3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits

SLT integrated circuit capacitor structure and methods

Liquid crystal display device and electronic device

3D semiconductor device and structure with high-k metal gate transistors

Semiconductor device and method for controlling semiconductor device

Assemblies containing PMOS decks vertically-integrated with NMOS decks, and methods of forming integrated assemblies