209309 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Applying interconnections to be used for carrying current between separate components within a device; Formation and after-treatment of dielectrics; Formation of thin functional dielectric layers in via holes or trenches
Sub-classes:MULTI-LINER TSV STRUCTURE AND METHOD FORMING SAME
#2MEMORY STRUCTURE INCLUDING LOW DIELECTRIC CONSTANT CAPPING LAYER
#3SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#4GUARD RING AND MANUFACTURING METHOD THEREOF
#5SEMICONDUCTOR DEVICE FABRICATING METHOD
#6MEMORY STRUCTURE
#7Multi-Liner TSV Structure and Method Forming Same
#8Conductive Interconnects and Methods of Forming Conductive Interconnects
#9Guard ring and manufacturing method thereof
#10Methods of forming an apparatus including laminate spacer structures
#11Metal oxide thin film transistor and manufacturing method thereof
#12Apparatuses including laminate spacer structures, and related memory devices, electronic systems, and methods
#13Semiconductor device and method for forming the same
#14Image sensor with dual trench isolation structures at different isolation structure depths
#15Dual-damascene formation with dielectric spacer and thin liner
#16Semiconductor device and method for forming the same
#17Via in substrate with deposited layer
#18Via in substrate with deposited layer
#19Method for manufacturing a semiconductor device having a stepped contact hole
#20Method of forming metal wiring in a semiconductor device
#21Method for manufacturing an integrated semiconductor device
#22Method for forming contact hole in semiconductor device
#23Method for cleaning substrate surface
#24Wiring structure for integrated circuit with reduced intralevel capacitance
#25Dry etching method using polymer mask selectively formed by CO gas
#26WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE
#27Method for cleaning substrate surface