H01L2224/02321 - CPC Classification Index

ClassID:

209410 ⎘

H01L2224/02321 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Redistribution layers [RDL] for bonding areas; Manufacturing methods of the redistribution layers Reworking

Recent Application in this class:

20250349627

2025-11-13

SACRIFICIAL TEST PAD

20250132208

2025-04-24

SACRIFICIAL TEST PAD

20250022851

2025-01-16

FLIP-CHIP STACKING STRUCTURES AND METHODS FOR FORMING THE SAME

20250022850

2025-01-16

FLIP-CHIP STACKING STRUCTURES AND METHODS FOR FORMING THE SAME

20230077469

2023-03-16

Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices

20230072507

2023-03-09

Redistribution layer metallic structure and method

20220302060

2022-09-22

SEMICONDUCTOR DEVICE HAVING A REDISTRIBUTION LINE

20220254755

2022-08-11

Flip-chip stacking structures and methods for forming the same

20210375702

2021-12-02

Display substrate and method for detecting broken fanout wire of display substrate

#10

20210159196

2021-05-27

Redistribution layer metallic structure and method

#11

20200395325

2020-12-17

Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices

#12

20200328153

2020-10-15

Forming bonding structures by using template layer as templates

#13

20200152589

2020-05-14

Semiconductor device having a redistribution line

#14

20200144208

2020-05-07

Redistribution layer metallic structure and method

#15

20190304939

2019-10-03

Redistribution layer metallic structure and method

#16

20190273067

2019-09-05

Semiconductor package having singular wire bond on bonding pads

#17

20190244948

2019-08-08

Electronic system having increased coupling by using horizontal and vertical communication channels

#18

20190067229

2019-02-28

Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices

#19

20190019769

2019-01-17

Method of pattern placement correction

#20

20190013289

2019-01-10

Semiconductor package device and method of manufacturing the same

#21

20180226369

2018-08-09

Method of pattern placement correction

#22

20180226342

2018-08-09

Forming bonding structures by using template layer as templates

#23

20180151525

2018-05-31

Redistribution layer structure and fabrication method therefor

#24

20180151519

2018-05-31

Method for manufacturing redistribution layer

#25

20180130784

2018-05-10

Electronic system having increased coupling by using horizontal and vertical communication channels

#26

20180114763

2018-04-26

Method for manufacturing a semiconductor structure

#27

20180102353

2018-04-12

Electronic system having increased coupling by using horizontal and vertical communication channels

#28

20180068965

2018-03-08

Conductive pad structure for hybrid bonding and methods of forming same

#29

20180006002

2018-01-04

Semiconductor chip package with resilient conductive paste post and fabrication method thereof

#30

20170040269

2017-02-09

Method of packaging semiconductor devices

#31

20160343679

2016-11-24

Conductive pad structure for hybrid bonding and methods of forming same

#32

20150262948

2015-09-17

Methods and apparatus of packaging semiconductor devices

#33

20150228597

2015-08-13

Copper post structure for wafer level chip scale package

#34

20150171050

2015-06-18

Conductive pad structure for hybrid bonding and methods of forming same

#35

20140252592

2014-09-11

Pad defined contact for wafer level package

#36

20130323884

2013-12-05

Three dimensional microelectronic components and fabrication methods for same

#37

20130316497

2013-11-28

THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME

#38

20130242500

2013-09-19

Integrated circuit chip using top post-passivation technology and bottom structure technology

#39

20130241025

2013-09-19

Electronic system having increased coupling by using horizontal and vertical communication channels

#40

20130020723

2013-01-24

Composite layered chip package

#41

20120313260

2012-12-13

Layered chip package and method of manufacturing same

#42

20120313259

2012-12-13

Layered chip package and method of manufacturing same

#43

20120156453

2012-06-21

CRACK REDUCTION AT METAL/ORGANIC DIELECTRIC INTERFACE

#44

20120056333

2012-03-08

Layered chip package and method of manufacturing same

#45

20120018874

2012-01-26

Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch

#46

20120013024

2012-01-19

Layered chip package and method of manufacturing same

#47

20110316141

2011-12-29

Layered chip package and method of manufacturing same

#48

20110316123

2011-12-29

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

#49

20110180932

2011-07-28

Method of manufacturing layered chip package

#50

20110169143

2011-07-14

Method for establishing and closing a trench of a semiconductor component

#51

20110018137

2011-01-27

Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus

#52

20100246152

2010-09-30

Integrated circuit chip using top post-passivation technology and bottom structure technology

#53

20100184257

2010-07-22

Method of manufacturing semiconductor device

#54

20090183906

2009-07-23

SUBSTRATE FOR MOUNTING DEVICE AND METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME, AND PORTABLE APPARATUS PROVIDED WITH THE SAME

#55