ClassID:

209427

H01L2224/024 - page 2 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Redistribution layers [RDL] for bonding areas Material of the insulating layers therebetween

Recent Application in this class:
#301
20100301459
2010-12-02

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

#302
20100295176
2010-11-25

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT

#303
20100283146
2010-11-11

Semiconductor structure

#304
20100248429
2010-09-30

METHOD FOR MANUFACTURING SEMICONDUCTOR MODULES

#305
20100246152
2010-09-30

Integrated circuit chip using top post-passivation technology and bottom structure technology

#306
20100244188
2010-09-30

Semiconductor device and manufacturing method thereof

#307
20100207270
2010-08-19

Semiconductor module, method for manufacturing semiconductor module, and portable device

#308
20100193950
2010-08-05

WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO

#309
20100187659
2010-07-29

Semiconductor device and method for manufacturing semiconductor device

#310
20100140752
2010-06-10

Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief

#311
20100116531
2010-05-13

Component with Mechanically Loadable Connecting Surface

#312
20100078798
2010-04-01

Insulation covering structure for a semiconductor element with a single die dimension and a manufacturing method thereof

#313
20100052164
2010-03-04

Wafer level package and method of manufacturing the same

#314
20100038779
2010-02-18

Semiconductor device

#315
20100035382
2010-02-11

Methods of making compliant semiconductor chip packages

#316
20100019384
2010-01-28

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

#317
20100013093
2010-01-21

Chip mounting

#318
20090315177
2009-12-24

Semiconductor package with joint reliability, entangled wires including insulating material

#319
20090278263
2009-11-12

RELIABILITY WCSP LAYOUTS

#320
20090273081
2009-11-05

Pad cushion structure and method of fabrication for Pb-free C4 integrated circuit chip joining

#321
20090219069
2009-09-03

Semiconductor integrated circuit device

#322
20090218685
2009-09-03

Semiconductor module and method of producing the same

#323
20090088536
2009-04-02

Heat-resistant resin paste and method for producing same

#324
20080272502
2008-11-06

Packaging board, rewiring, roughened conductor for semiconductor module of a portable device, and manufacturing method therefor

#325
20080265410
2008-10-30

Wafer level package

#326
20080261352
2008-10-23

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

#327
20080185738
2008-08-07

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

#328
20080174026
2008-07-24

SEMICONDUCTOR DEVICE

#329
20080174014
2008-07-24

Semiconductor device

#330
20080174011
2008-07-24

Semiconductor structure and method for forming the same

#331
20080145973
2008-06-19

Method of manufacturing wafer level chip size package

#332
20080119037
2008-05-22

Method for manufacturing semiconductor device

#333
20080099907
2008-05-01

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

#334
20080099900
2008-05-01

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

#335
20080067663
2008-03-20

Wafer level chip package and a method of fabricating thereof

#336
20080012129
2008-01-17

Semiconductor device and method of producing the same

#337
20080012115
2008-01-17

Methods and apparatus for packaging integrated circuit devices

#338
20080006910
2008-01-10

Semiconductor device and method for manufacturing semiconductor device

#339
20070284755
2007-12-13

Semiconductor device, manufacturing method of the semiconductor device, and mounting method of the semiconductor device

#340
20070284721
2007-12-13

Semiconductor device and method for producing the semiconductor device

#341
20070232053
2007-10-04

Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

#342
20070184643
2007-08-09

Methods of forming metal layers using multi-layer lift-off patterns

#343
20070176240
2007-08-02

Wafer level package having floated metal line and method thereof

#344
20070164431
2007-07-19

WAFER LEVEL CHIP SCALE PACKAGE HAVING REROUTING LAYER AND METHOD OF MANUFACTURING THE SAME

#345
20060261476
2006-11-23

Microelectronic assemblies having compliant layers

#346
20060246635
2006-11-02

Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

#347
20060237836
2006-10-26

Microelectronic assemblies having compliant layers

#348
20060223303
2006-10-05

Semiconductor device and method of manufacturing the same

#349
20060194365
2006-08-31

Microelectronic assemblies having compliancy

#350
20060091539
2006-05-04

Semiconductor device, circuit board, electro-optic device, electronic device

#351
20060006480
2006-01-12

Semiconductor integrated circuit device

#352
20050205977
2005-09-22

Methods and apparatus for packaging integrated circuit devices

#353
20050170602
2005-08-04

Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

#354
20050133914
2005-06-23

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

#355
20050064624
2005-03-24

Method of manufacturing wafer level chip size package

#356
20050020052
2005-01-27

Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

#357
16176078
2019-12-31

Patterning polymer layer to reduce stress

#358
15840842
2018-09-25

Stress relief solutions on WLCSP large/bulk copper plane design

#359
15662279
2018-12-18

Package structure and method of forming the same

#360
14837712
2016-12-13

Wafer level package (WLP) and method for forming the same