ClassID:

209442

H01L2224/0331 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods by local deposition of the material of the bonding area in liquid form

Sub-classes:
Recent Application in this class:
#1
20250379167
2025-12-11

LIQUID METAL INTERCONNECTS FOR POWER SEMICONDUCTOR MODULES

#2
20250167157
2025-05-22

MICROELECTRONIC DEVICE OBTAINED BY 3D INTEGRATION AND CORRESPONDING PRODUCTION METHOD

#3
20230275065
2023-08-31

Semiconductor device and method of forming insulating layers around semiconductor die

#4
20230005849
2023-01-05

Semiconductor structure and manufacturing method thereof

#5
20210057378
2021-02-25

Semiconductor device and method of forming insulating layers around semiconductor die

#6
20210035932
2021-02-04

Integrated circuit backside metallization

#7
20200381380
2020-12-03

Semiconductor package having a laser-activatable mold compound

#8
20200350268
2020-11-05

WIRE BONDING STRUCTURE AND METHOD OF MANUFACTURING THE SAME

#9
20200203295
2020-06-25

Integrated circuit backside metallization

#10
20190067241
2019-02-28

Semiconductor device and method of forming insulating layers around semiconductor die

#11
20180211943
2018-07-26

Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same

#12
20180174999
2018-06-21

Die sidewall interconnects for 3D chip assemblies

#13
20180068976
2018-03-08

Semiconductor device and method of forming insulating layers around semiconductor die

#14
20170250158
2017-08-31

Semiconductor device and method of forming insulating layers around semiconductor die

#15
20170194272
2017-07-06

Method of manufacturing a layer structure having partially sealed pores

#16
20170012081
2017-01-12

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

#17
20160049390
2016-02-18

Multiple bond via arrays of different wire heights on a same substrate

#18
20150380341
2015-12-31

Conductor structure for three-dimensional semiconductor device

#19
20150325538
2015-11-12

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

#20
20130277837
2013-10-24

Controlled solder-on-die integrations on packages and methods of assembling same

#21
20130009286
2013-01-10

SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME

#22
20120164789
2012-06-28

Three-dimensional semiconductor device

#23
20100071946
2010-03-25

Electronic component mounting structure

#24
20090039507
2009-02-12

Electronic element that includes multilayered bonding interface between first electrode having aluminum-containing surface and second electrode composed of metal nanoparticle sintered body

#25
20080258309
2008-10-23

Three-dimensional semiconductor device

#26
20080150154
2008-06-26

METHOD FOR FABRICATING A CIRCUIT

#27
16038372
2019-05-28

Protective layers for high-yield printed electronic devices

#28
14953456
2017-04-11

Method of manufacturing an electronic device having a contact pad with partially sealed pores