ClassID:

209441

H01L2224/033 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods by local deposition of the material of the bonding area

Sub-classes:
Recent Application in this class:
#1
20260052992
2026-02-19

HYBRID BONDING USING STRESS-RELIEF DUMMY PADS AND METHODS OF FORMING AND USING THE SAME

#2
20250329673
2025-10-23

Direct Wire Reveal Package

#3
20250293186
2025-09-18

BOND PAD STRUCTURE COUPLED TO MULTIPLE INTERCONNECT CONDUCTIVE\ STRUCTURES THROUGH TRENCH IN SUBSTRATE

#4
20250239549
2025-07-24

SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THEREOF

#5
20250157957
2025-05-15

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

#6
20250149474
2025-05-08

Selective Dielectric Capping for Hybrid Bonding

#7
20230395540
2023-12-07

BOND PAD STRUCTURE COUPLED TO MULTIPLE INTERCONNECT CONDUCTIVE\ STRUCTURES THROUGH TRENCH IN SUBSTRATE

#8
20230387052
2023-11-30

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

#9
20230207530
2023-06-29

Stacked semiconductor structure and method

#10
20230170318
2023-06-01

SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR PACKAGING STRUCTURE

#11
20230061418
2023-03-02

Semiconductor package and method of manufacturing same

#12
20220344291
2022-10-27

Bond pad structure coupled to multiple interconnect conductive\ structures through trench in substrate

#13
20220181269
2022-06-09

Chip packaging method and chip packaging structure

#14
20210225813
2021-07-22

Stacked semiconductor structure and method

#15
20200312791
2020-10-01

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#16
20200168584
2020-05-28

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

#17
20200144202
2020-05-07

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#18
20200075556
2020-03-05

Stacked semiconductor structure and method

#19
20190123026
2019-04-25

Stacked semiconductor structure and method

#20
20180350756
2018-12-06

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#21
20180012869
2018-01-11

Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods

#22
20170323869
2017-11-09

Stacked semiconductor structure and method

#23
20160210495
2016-07-21

Connection pads for a fingerprint sensing device

#24
20160163666
2016-06-09

Semiconductor device and manufacturing method for the same

#25
20160155725
2016-06-02

Stacked semicondcutor structure and method

#26
20150333024
2015-11-19

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

#27
20150294955
2015-10-15

Stacked semiconductor structure and method

#28
20150187636
2015-07-02

Semiconductor device and manufacturing method thereof

#29
20150187608
2015-07-02

DIE PACKAGE ARCHITECTURE WITH EMBEDDED DIE AND SIMPLIFIED REDISTRIBUTION LAYER

#30
20150179593
2015-06-25

Low z-height package assembly

#31
20150050779
2015-02-19

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

#32
20140342507
2014-11-20

Fabrication method of semiconductor package

#33
20140191406
2014-07-10

Manufacturing method for semiconductor package, semiconductor package, and semiconductor device

#34
20130256875
2013-10-03

Semiconductor package, package structure and fabrication method thereof

#35
20130087915
2013-04-11

Copper Stud Bump Wafer Level Package

#36
20120248621
2012-10-04

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

#37
15221372
2017-10-24

Methods for repackaging copper wire-bonded microelectronic die

#38
14331624
2016-02-02

Method for forming semiconductor layout