209446 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods by local deposition of the material of the bonding area in solid form
Sub-classes:Multiple plated via arrays of different wire heights on same substrate
#2Multiple bond via arrays of different wire heights on a same substrate
#3METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS
#4Conductive connections, structures with such connections, and methods of manufacture
#5Multiple bond via arrays of different wire heights on a same substrate
#6Multiple bond via arrays of different wire heights on a same substrate
#7Conductive connections, structures with such connections, and methods of manufacture
#8Conductive connections, structures with such connections, and methods of manufacture
#9Semiconductor module system having encapsulated through wire interconnect (TWI)
#10Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI)
#11Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)
#12System with semiconductor components having encapsulated through wire interconnects (TWI)
#13Face-to-face (F2F) hybrid structure for an integrated circuit
#14Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)
#15Semiconductor components having encapsulated through wire interconnects (TWI)