Chip embedding package with solderable electric contact

Semiconductor structure and manufacturing method thereof

Method of manufacturing a semiconductor device

Semiconductor device and method of manufacture

Conductive traces in semiconductor devices and methods of forming same

Method for singulating packaged integrated circuits and resulting structures

Multi-chip structure and method of forming same

Fingerprint sensor device and method

Vertical semiconductor device with thinned substrate

Display apparatus including a micro light-emitting diode

Connector structure and method of forming same

Bump structure, display device including a bump structure, and method of manufacturing a bump structure

Fan-out package structure and method for forming the same

Semiconductor package

Fingerprint sensor and manufacturing method thereof

Chip package assembly with power management integrated circuit and integrated circuit die

Semiconductor device and method of making wafer level chip scale package

Apparatus for stacking semiconductor chips in a semiconductor package

BUMP-EQUIPPED ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING BUMP-EQUIPPED ELECTRONIC COMPONENT

Multichip modules and methods of fabrication

Reliable passivation for integrated circuits

Chip part and method for manufacturing a chip part

Methods for making multi-die package with bridge layer

Hybrid-on-chip and package antenna

Semiconductor device with reduced parasitic drain-gate capacitance and method of manufacturing the same

Power device on bulk substrate

Interconnect structures with polymer core

Method of controlling bump height variation

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Inter-chip alignment

Connector structures of integrated circuits

Device with optimized thermal characteristics

Semiconductor substrate having stress-absorbing surface layer

Package structure and method for forming the same

Methods of manufacturing an integrated circuit having stress tuning layer

Wiring substrate and semiconductor device

Fabrication method of wafer level packaging semiconductor package with sandwich structure of support plate isolation layer and bonding layer

Chip part and method of making the same

Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area

Method of producing optoelectronic component with integrated protection diode

Semiconductor devices and methods of manufacture thereof

Semiconductor device processing method for material removal

Fabricating method for wafer-level packaging

Sawing underfill in packaging processes

Testing of semiconductor chips with microbumps

Integrated circuit structures with recessed conductive contacts for package on package

Electronic device and electronic apparatus

SEMICONDUCTOR DEVICE

Backside contacts for integrated circuit devices

Bridge interconnection with layered interconnect structures

Methods for forming interconnect assemblies with probed bond pads

Fabrication method of semiconductor package

Semiconductor device and method for manufacturing the same

Power and ground design for through-silicon via structure

Method of fabricating 3-dimensional fan-out structure

Multi-chip package with interconnects extending through logic chip

Mechanisms for forming post-passivation interconnect structure

Semiconductor devices including a through via structure and methods of forming the same

Embedding thin chips in polymer

Dicing method for wafer-level packaging and semiconductor chip with dicing structure adapted for wafer-level packaging

Test probe substrate

Test probe substrate

Apparatus and methods for electrical overstress protection

Integrated LED and LED driver units and methods for fabricating the same

Semiconductor device and portable apparatus using the same

Fan-out stacked system in package (SIP) and the methods of making the same

Method for self-aligned solder reflow bonding and devices obtained thereof

Structures and methods for low temperature bonding using nanoparticles

Multi-strike process for bonding packages and the packages thereof

Via structure for packaging and a method of forming

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Semiconductor structure and manufacturing method thereof

Lid structure for a semiconductor device package and method for forming the same

Semiconductor device

Ball grid array package with protective circuitry layout and a substrate utilized in the package

Underfill control structures and method

Semiconductor image sensor module and method of manufacturing the same

Thin fan-out multi-chip stacked packages and the method for manufacturing the same

Semiconductor device manufacturing method and semiconductor wafer

Method and structure for wafer-level packaging

Semiconductor device and semiconductor device manufacturing method

System and method for an improved interconnect structure

Packaging substrate and electronic package having the same

SOI wafers with buried dielectric layers to prevent Cu diffusion

Semiconductor package

Semiconductor devices having through electrodes and methods of manufacturing the same

Structure for die probing

Multi-layer power converter with devices having reduced lateral current

Semiconductor packaging structure and method

Semiconductor package

Nanowires for pillar interconnects

Semiconductor device

Flip chip package structure and fabrication process thereof

Semiconductor device with a bump contact on a TSV comprising a cavity and method of producing such a semiconductor device

Semiconductor structure

Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same

Self-aligned under bump metal

Method of forming metal pads with openings in integrated circuits including forming a polymer extending into a metal pad

Contact pad for semiconductor devices

Integrated circuit

Methods of forming metal pad structures over TSVS to reduce shorting of upper metal layers

Display panel and display device including the same

Integrated circuit packages with temperature sensor traces

Integrated circuit structure and method for reducing polymer layer delamination

Method for arranging electronic switching elements, electronic switching arrangement and use of a carrier having a bonding layer

Bonding structure and method for producing bonding structure

Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip

Multilayer pillar for reduced stress interconnect and method of making same

Flip chip assembly with connected component

Packages with molding structures and methods of forming the same

Fan-out wafer-level packaging using metal foil lamination

Capacitor formed on heavily doped substrate

SOLDER COMPOSITION AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Semiconductor device including multiple semiconductor chips

Semiconductor devices and methods of manufacture thereof

Wafer-level chip-scale package with redistribution layer

Transient interface gradient bonding for metal bonds

Electronic component package and electronic device including the same

Chip-size, double side connection package and method for manufacturing the same

Semiconductor device and method of manufacturing the same

Methods of forming connector pad structures, interconnect structures, and structures thereof

Semiconductor device having an encapsulated front side and interposer and manufacturing method thereof

Structure for stacked logic performance improvement

Semiconductor device and manufacturing method thereof

Integrated circuit package substrate

Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices

Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof

Integrated circuit packages and methods of forming same

Extrusion-resistant solder interconnect structures and methods of forming

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

Electrical package including bimetal lid

Electrical package including bimetal lid

Fan-out semiconductor package and electronic device including the same

Conductive paths through dielectric with a high aspect ratio for semiconductor devices

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Multi-die fine grain integrated voltage regulation

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Three layer stack structure

Split ball grid array pad for multi-chip modules

Mechanisms for forming hybrid bonding structures with elongated bumps

Metal bump joint structure

Electronic component package and electronic device including the same

COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME

Organic thin film passivation of metal interconnections

Post-passivation interconnect structure and method of forming same

Method and apparatus for forming backside die planar devices and saw filter

Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology

Semiconductor structure and manufacturing method thereof

Chip packages and methods of manufacture thereof

Package with solder regions aligned to recesses

Methods and apparatus of guard rings for wafer-level-packaging

Carrier ultra thin substrate

Semiconductor packages with an intermetallic layer

Multilayer pillar for reduced stress interconnect and method of making same

Fabrication method of packaging substrate

Interconnect structures and methods for fabricating interconnect structures

Semiconductor device and method of making a semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method of controlling warpage in reconstituted wafer

Pad structure design in fan-out package

Fan-out semiconductor package and electronic device including the same

Semiconductor structure and method of manufacturing the same

Semiconductor device and method of using a standardized carrier in semiconductor packaging

Solenoid inductor

High-bandwidth memory application with controlled impedance loading

Coating electronic component

Chip-stacked semiconductor package and method of manufacturing the same

Semiconductor device with discrete blocks

Semiconductor package

Electronic device, electronic part, and solder

INTEGRATED CIRCUIT DEVICE HAVING THROUGH VIA BASED ALIGNMENT KEYS AND METHODS OF FORMING THE SAME

Shielded package assemblies with integrated capacitor

Logic die and other components embedded in build-up layers

Power management application of interconnect substrates

Integrated circuit package comprising surface capacitor and ground plane

Solder bump placement for grounding in flip chip amplifiers

Pad structure for front side illuminated image sensor

Solder bump placement for emitter-ballasting in flip chip amplifiers

Printed circuit boards and semiconductor packages including the same

Solderless interconnection structure and method of forming same

Isolation device

Solder bump placement for thermal management in flip chip amplifiers

Semiconductor devices with bump allocation

Wafer-level packaging sensing device and method for forming the same

Semiconductor device and package including solder bumps with strengthened intermetallic compound

Method of manufacturing a semiconductor device having reduced on-state resistance and structure

Semiconductor device

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME

Semiconductor chip with patterned underbump metallization and polymer film

Semiconductor die contact structure and method

Surface finishes for interconnection pads in microelectronic structures

Semiconductor device and method

Semiconductor device and manufacturing method thereof

Semiconductor device

Integrated circuit package

Semiconductor structure and manufacturing method thereof

Semiconductor device and method for manufacturing the same

Wiring substrate and semiconductor device

Interconnect structures for fine pitch assembly of semiconductor structures and related techniques

Semiconductor chip including a plurality of pads

Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package

Configurable routing for packaging applications

Semiconductor die connection system and method

Semiconductor device and manufacturing method therefor

Wafer level package (WLP) and method for forming the same

Semiconductor device and method of forming a curved image sensor

Semiconductor device and a method of manufacturing the same

Package structures and method of forming the same

Semiconductor package structure and method for forming the same

Semiconductor device and method of forming modular 3D semiconductor package with horizontal and vertical oriented substrates

Method for bonding a chip to a wafer

Method of manufacturing electronic component module and electronic component module

Designs and methods for conductive bumps

Cu pillar bump with L-shaped non-metal sidewall protection structure

PACKAGE STRUCTURE, CHIP STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor devices with solder-based connection terminals and method of forming the same

Methods and apparatus for solder connections

Semiconductor devices with redistribution pads

Semiconductor package

Bonding pad structure, bonding ring structure, and MEMS device packaging method

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Dummy metal with zigzagged edges

Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Augmented capacitor structure for high quality (Q)-factor radio frequency (RF) applications

Laser marking in packages

Fan-out package structure having embedded package substrate

Semiconductor device and control method for the same

Semiconductor device including semiconductor chip, wiring, conductive material, and contact part

Semiconductor device

Collars for under-bump metal structures and associated systems and methods

Surface mount high-frequency circuit

Semiconductor apparatus, stacked semiconductor apparatus and encapsulated stacked-semiconductor apparatus each having photo-curable resin layer

System-level packaging structures

Fully molded miniaturized semiconductor module

Three-dimensional integrated circuit integration

Power overlay structure and method of making same

Apparatus, system and method for collecting a target material

Semiconductor devices and packages and methods of forming semiconductor device packages

Semiconductor package and method of forming the same

Anchored interconnect

Conductive contacts having varying widths and method of manufacturing same

Semiconductor device

Semiconductor chip package and method of manufacturing the same

Method of making layered structure with metal layers using resist patterns and electrolytic plating

Semiconductor package with integrated semiconductor devices and passive component

Semiconductor package embedded with plurality of chips and method of manufacturing the same

Electronic apparatus and method for fabricating the same

Semiconductor device and manufacturing method thereof

Bump structure having a side recess and semiconductor structure including the same

Semiconductor packaging and manufacturing method thereof

Method of manufacturing fan-out type wafer level package

Semiconductor chip, semiconductor package including the same, and method of fabricating the same

Semiconductor package and manufacturing method thereof

Semiconductor device having a conductive via structure

Semiconductor device

Sintered conductive matrix material on wire bond

Semiconductor devices and methods of manufacturing the same

Semiconductor device

Method of manufacturing semiconductor device and semiconductor device

High quality electrical contacts between integrated circuit chips

Semiconductor device and method of manufacturing thereof

Semiconductor device

Electrostatic discharge protection apparatus and process

INTEGRATED CIRCUIT PACKAGE

Electronic device having a redistribution area

Semiconductor apparatus, method for manufacturing the same, electronic device, and moving body

Semiconductor die attachment with embedded stud bumps in attachment material

Method for fabricating glass substrate package

Structures and methods for low temperature bonding using nanoparticles

Electronic apparatus and method for manufacturing electronic apparatus

Method of fabricating chip package with laser

Scheme for connector site spacing and resulting structures

Stress tuning for reducing wafer warpage

Semiconductor package and manufacturing method thereof

Semiconductor device, manufacturing method thereof, and electronic apparatus

Photosensitive element, laminate, permanent mask resist, method for producing same, and method for producing semiconductor package

Method of assembly semiconductor device with through-package interconnect

Printed circuit board (PCB), method of manufacturing the PCB, and method of manufacturing semiconductor package using the PCB

Three dimensional integrated circuits stacking approach

Integrated fan-out package structures with recesses in molding compound

Semiconductor device and semiconductor package

Semiconductor device

Semiconductor package and method of forming the same

Methods and structures to repair device warpage

Method of packaging semiconductor devices

Method of manufacturing semiconductor device and semiconductor device

FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA

Fan-out semiconductor package and method of manufacturing the same

Capacitor in post-passivation structures and methods of forming the same

Semiconductor device with insulation layers

Photoresist cleaning composition used in photolithography and a method for treating substrate therewith

Semiconductor device having a plurality of chips being stacked

Semiconductor package structure and method for forming the same

Multi-device package and manufacturing method thereof

Bonding structure for semiconductor package and method of manufacturing the same

Low pressure sintering powder

Formation of solder and copper interconnect structures and associated techniques and configurations

Semiconductor devices and methods of forming thereof

Packaging devices and methods of manufacture thereof

Battery protection package and process of making the same