H01L2224/11823 - CPC Classification Index

ClassID:

209670 ⎘

H01L2224/11823 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Manufacturing methods; Post-treatment of the bump connector; Applying permanent coating, e.g. in-situ coating Immersion coating, e.g. in a solder bath

Recent Application in this class:

20240332033

2024-10-03

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SEMICONDUCTOR DEVICE AND MOUNTING ASSEMBLY

20240304581

2024-09-12

Coating of Nanowires

20230090693

2023-03-23

DIPPING APPARATUS, DIE BONDING APPARATUS, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

20200126937

2020-04-23

Semiconductor device and bump formation process

20190123027

2019-04-25

Package-on-package (PoP) structure including stud bulbs

20180247907

2018-08-30

Semiconductor device and bump formation process

20180047709

2018-02-15

Package-on-package (PoP) structure including stud bulbs

20170025391

2017-01-26

Package on-package (PoP) structure including stud bulbs

20170005051

2017-01-05

Semiconductor device and bump formation process

#10

20160260646

2016-09-08

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

#11

20160218076

2016-07-28

Semiconductor device having a cylindrical shaped conductive portion

#12

20160104685

2016-04-14

Improving the strength of micro-bump joints

#13

20160049371

2016-02-18

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

#14

20150380371

2015-12-31

Method of forming an integrated circuit device including a pillar capped by barrier layer

#15

20150279797

2015-10-01

Manufacture of coated copper pillars

#16

20150214182

2015-07-30

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

#17

20150171041

2015-06-18

CHIP ELEMENT AND CHIP PACKAGE

#18

20150132889

2015-05-14

Package on-Package (PoP) structure including stud bulbs and method

#19

20150104903

2015-04-16

Treating copper surfaces for packaging

#20

20150037936

2015-02-05

Strength of micro-bump joints

#21

20140342546

2014-11-20

Copper pillar bump with cobalt-containing sidewall protection layer

#22

20140227831

2014-08-14

Front side copper post joint structure for temporary bond in TSV application

#23

20140206145

2014-07-24

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

#24

20140182912

2014-07-03

Packaging substrate

#25

20140124924

2014-05-08

Integrated circuit device including a copper pillar capped by barrier layer and method of forming the same

#26

20130307144

2013-11-21

Three-dimensional chip stack and method of forming the same

#27

20130295762

2013-11-07

Cu pillar bump with electrolytic metal sidewall protection

#28

20130256910

2013-10-03

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

#29

20130134588

2013-05-30

Package-on-package (PoP) structure including stud bulbs and method

#30

20130077272

2013-03-28

Structure design for 3DIC testing

#31

20120273945

2012-11-01

Integrated circuit device including a copper pillar capped by barrier layer

#32

20120267781

2012-10-25

Mechanisms for forming copper pillar bumps using patterned anodes

#33

20120091577

2012-04-19

Copper pillar bump with cobalt-containing sidewall protection

#34

20120043654

2012-02-23

Mechanisms for forming copper pillar bumps using patterned anodes

#35

20120007231

2012-01-12

Method of forming Cu pillar capped by barrier layer

#36

20110304042

2011-12-15

Copper bump structures having sidewall protection layers

#37

20110291262

2011-12-01

Strength of micro-bump joints

#38

20110260317

2011-10-27

Cu pillar bump with electrolytic metal sidewall protection

#39

20110226841

2011-09-22

ROOM TEMPERATURE DIRECT METAL-METAL BONDING

#40

20110186989

2011-08-04

Semiconductor Device and Bump Formation Process

#41

20110111561

2011-05-12

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

#42

20110086505

2011-04-14

METALLIC BUMP STRUCTURE WITHOUT UNDER BUMP METALLURGY AND A MANUFACTURING METHOD THEREOF

#43

20110084386

2011-04-14

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

#44

20110049706

2011-03-03

Front side copper post joint structure for temporary bond in TSV application

#45

20100320560

2010-12-23

Metallic Bump Structure Without Under Bump Metallurgy And a Manufacturing Method Thereof

#46

20100084763

2010-04-08

Metallic bump structure without under bump metallurgy and manufacturing method thereof

#47

20100059897

2010-03-11

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

#48

20090275191

2009-11-05

Method and apparatus for electrostatic discharge protection using a temporary conductive coating

#49

14332690

2015-12-22

Devices employing semiconductor die having hydrophobic coatings, and related cooling methods