Patents-Review.com
ClassID:

209673 ⎘

H01L2224/11826 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Manufacturing methods; Post-treatment of the bump connector; Applying permanent coating, e.g. in-situ coating Physical vapour deposition [PVD], e.g. evaporation, or sputtering

Recent Application in this class:
#1
20250372559
2025-12-04

SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION

 #2
20240071973
2024-02-29

SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION

 #3
20230282605
2023-09-07

Solder based hybrid bonding for fine pitch and thin BLT interconnection

 #4
20200203297
2020-06-25

Interconnect structures for preventing solder bridging, and associated systems and methods

 #5
20190326241
2019-10-24

Mechanisms for forming post-passivation interconnect structure

 #6
20190198470
2019-06-27

Interconnect structures for preventing solder bridging, and associated systems and methods

 #7
20170200687
2017-07-13

Mechanisms for forming post-passivation interconnect structure

 #8
20160181216
2016-06-23

Reducing solder pad topology differences by planarization

 #9
20160128193
2016-05-05

Systems, methods and devices for inter-substrate coupling

 #10
20160027756
2016-01-28

Semiconductor device

 #11
20160005705
2016-01-07

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

 #12
20150132940
2015-05-14

Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same

 #13
20140327101
2014-11-06

Image pickup device and method for producing the same

 #14
20140246770
2014-09-04

Copper nanorod-based thermal interface material (TIM)

 #15
20140206145
2014-07-24

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

 #16
20140110835
2014-04-24

Bump package and methods of formation thereof

 #17
20130130496
2013-05-23

Semiconductor apparatus

 #18
20120235301
2012-09-20

Semiconductor apparatus including a metal alloy between a first contact and a second contact

 #19
20120018880
2012-01-26

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

 #20
20110226841
2011-09-22

ROOM TEMPERATURE DIRECT METAL-METAL BONDING

 #21
20110147177
2011-06-23

Structure, electronic device, and method for fabricating a structure

 #22
20110111561
2011-05-12

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

 #23
20110095420
2011-04-28

Semiconductor device and method of manufacturing semiconductor device

 #24
20100093229
2010-04-15

Microelectronic contact structure

 #25
20100059897
2010-03-11

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

 #26
20090275191
2009-11-05

Method and apparatus for electrostatic discharge protection using a temporary conductive coating

 #27
20050025942
2005-02-03

Method of bonding semiconductor devices

 #28
14332690
2015-12-22

Devices employing semiconductor die having hydrophobic coatings, and related cooling methods