209685 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Manufacturing methods; Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
SEMICONDUCTOR DEVICE ASSEMBLY WITH SACRIFICIAL PILLARS AND METHODS OF MANUFACTURING SACRIFICIAL PILLARS
#2Method for Forming Semiconductor Package and Semiconductor Package
#3SEMICONDUCTOR STRUCTURE
#4SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#5Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
#6SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#7SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
#8Electroplated indium bump stacks for cryogenic electronics
#9SEMICONDUCTOR CONDUCTIVE PILLAR DEVICE AND METHOD
#10BUMP COPLANARITY FOR DIE-TO-DIE AND OTHER APPLICATIONS
#11PACKAGE SUBSTRATE
#12Semiconductor structure having polygonal bonding pad
#13Method of manufacturing semiconductor structure having polygonal bonding pad
#14ELECTRONIC PACKAGING ARCHITECTURE WITH CUSTOMIZED VARIABLE METAL THICKNESS ON SAME BUILDUP LAYER
#15Semiconductor structure and semiconductor die
#16SN-BI-IN-BASED LOW MELTING-POINT JOINING MEMBER, PRODUCTION METHOD THEREFOR, SEMICONDUCTOR ELECTRONIC CIRCUIT, AND MOUNTING METHOD THEREFOR
#17Electroplated indium bump stacks for cryogenic electronics
#18Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
#19Method for forming semiconductor package and semiconductor package
#20Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
#21Semiconductor device and manufacturing method thereof
#22Alternative integration for redistribution layer process
#23Semiconductor package
#24SEMICONDUCTOR DEVICE
#25SEMICONDUCTOR DEVICE HAVING BUMP STRUCTURES AND SEMICONDUCTOR PACKAGE HAVING THE SAME
#26Semiconductor package
#27Mechanisms for forming post-passivation interconnect structure
#28Tall and fine pitch interconnects
#29Tall and fine pitch interconnects
#30Tooling for coupling multiple electronic chips
#31Mechanisms for forming post-passivation interconnect structure
#32Extrusion-resistant solder interconnect structures and methods of forming
#33Tooling for coupling multiple electronic chips
#34Wafer to wafer bonding process and structures
#35Semiconductor package
#36Methods of fabricating semiconductor chip solder structures
#37Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
#38Semiconductor device
#39Semiconductor package
#40Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#41Chip package and method for forming the same
#42Chip package having a patterned conducting plate and method for forming the same
#43Stack of semiconductor structures and corresponding manufacturing method
#44Method of making a pillar structure having a non-metal sidewall protection structure
#45Pillar bumps and process for making same
#46Techniques for fabricating fine-pitch micro-bumps
#47Method of making a conductive pillar bump with non-metal sidewall protection structure
#48Front side copper post joint structure for temporary bond in TSV application
#49IC wafer having electromagnetic shielding effects and method for making the same
#50Extrusion-resistant solder interconnect structures and methods of forming
#51Method for self-assembly of substrates and devices obtained thereof
#52Controlled collapse chip connection (C4) structure and methods of forming
#53Stack of semiconductor structures and corresponding manufacturing method
#54Etching solution for copper or copper alloy
#55Bumping process and structure thereof
#56Printed circuit board and method for manufacturing the same
#57SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE
#58METHODS OF FORMING CONNECTION BUMP OF SEMICONDUCTOR DEVICE
#59Methods of fabricating semiconductor chip solder structures
#60Method and system for forming conductive bumping with copper interconnection
#61Coaxial solder bump support structure
#62Bumping process and structure thereof
#63SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME
#64Copper pillar bump with non-metal sidewall protection structure and method of making the same
#65Mechanisms for forming copper pillar bumps using patterned anodes
#66Etchant and method for manufacturing semiconductor device using same
#67IC wafer having electromagnetic shielding effects and method for making the same
#68Shared Electrostatic Discharge Protection For Integrated Circuits, Integrated Circuit Assemblies And Methods For Protecting Input/Output Circuits
#69Dummy metal design for packaging structures
#70Bump structure and manufacturing method thereof
#71Solder bump connections
#72Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
#73METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME
#74Semiconductor package
#75Method and system for forming conductive bumping with copper interconnection
#76SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#77Semiconductor device having pad structure with stress buffer layer
#78Pillar bumps and process for making same
#79Mechanisms for forming copper pillar bumps using patterned anodes
#80CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT
#81PATTERNED CONTACT
#82Cu pillar bump with non-metal sidewall protection structure
#83Inverse chip connector
#84Dummy metal design for packaging structures
#85Cu pillar bump with non-metal sidewall protection structure
#86Pin-type chip tooling
#87Rigid-backed, membrane-based chip tooling
#88CHIP PACKAGE
#89Method of fabricating a conductive post on an electrode
#90Semiconductor chip with a bonding pad having contact and test areas
#91SEMICONDUCTOR DEVICE, CHIP-ON-CHIP MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE CHIP-ON-CHIP MOUNTING STRUCTURE
#92Contact-based encapsulation
#93Chip having a metal pillar structure
#94Semiconductor device and method for manufacturing same
#95Front side copper post joint structure for temporary bond in TSV application
#96Manufacturing method of semiconductor device including Au bump on seed film
#97METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN EVEN COATING THICKNESS USING ELECTRO-LESS PLATING AND RELATED DEVICE
#98Coaxial through chip connection
#99Method of manufacturing semiconductor device
#100Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#101SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
#102Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers
#103Methods of forming solder connections and structure thereof
#104Method and system for forming conductive bumping with copper interconnection
#105Semiconductor package and methods of manufacturing the same
#106Method for fabricating electrical bonding pads on a wafer
#107Semiconductor device
#108Manufacturing method of semiconductor integrated device with inverting plating cup
#109Bonding method of semiconductor and laminated structure fabricated thereby
#110Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes
#111Structure and method for fabricating flip chip devices
#112SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING BOAC/COA
#113Chip assembly with interconnection by metal bump
#114Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device
#115Chip package
#116Copper die bumps with electromigration cap and plated solder
#117Voltage regulator integrated with semiconductor chip
#118Systems and methods to passivate on-die redistribution interconnects
#119Electrical interconnection structure formation
#120METHODS OF FORMING SOLDER CONNECTIONS AND STRUCTURE THEREOF
#121Methods of forming solder connections and structure thereof
#122Method of forming a bump and a connector structure having the bump
#123Chip package and method for fabricating the same
#124CHIP CONNECTOR
#125Tooling for coupling multiple electronic chips
#126Semiconductor chip with bond area
#127Coaxial through chip connection
#128Pin-type chip tooling
#129Damascene patterning of barrier layer metal for C4 solder bumps
#130Electrical interconnection structure formation
#131Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
#132Metal pad or metal bump over pad exposed by passivation layer
#133Technique for efficiently patterning an underbump metallization layer using a dry etch process
#134Technique for forming a copper-based contact layer without a terminal metal
#135Coaxial through chip connection
#136Post-attachment chip-to-chip connection
#137Rigid-backed, membrane-based chip tooling
#138Through chip connection
#139Inverse chip connector
#140Chip connector
#141Profiled contact
#142Patterned contact
#143Contact-based encapsulation
#144Membrane-based chip tooling
#145Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes
#146Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#147Damascene patterning of barrier layer metal for C4 solder bumps
#148Titanium stripping solution
#149Bath and method for high rate copper deposition
#150Bond pad techniques for integrated circuits
#151Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer
#152Method of manufacturing a semiconductor structure