209771 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; High density interconnect [HDI] connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector Shape
Sub-classes:SEMICONDUCTOR PACKAGE
#2METHODS OF FORMING BONDING STRUCTURES
#3Integrated Circuit Packages and Methods of Forming the Same
#4ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
#5REDISTRIBUTION LAYER STRUCTURE FOR HIGH-DENSITY SEMICONDUCTOR PACKAGE ASSEMBLY
#6SEMICONDUCTOR PACKAGE
#7SEMICONDUCTOR PACKAGE
#8SEMICONDUCTOR PACKAGE WITH OPTICAL BRIDGE AND METHOD OF MANUFACTURING THE SAME
#9LEADING POINT OF DISCHARGE STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION AND METHODS OF FORMING THE SAME
#10SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
#11DIE AND PACKAGE STRUCTURE
#12METHODS OF FORMING BONDING STRUCTURES
#13STACKED INTEGRATED CIRCUITS WITH REDISTRIBUTION LINES
#14FAN-OUT PACKAGE HAVING BALL GRID ARRAY SUBSTRATE WITH SIGNAL AND POWER METALLIZATION
#15LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME
#16MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THROUGH DIELECTRIC VIA
#17Package and package-on-package structure having elliptical columns and ellipsoid joint terminals
#18Semiconductor device structure with composite bottle-shaped through silicon via
#19Semiconductor device structure with composite bottle-shaped through silicon via and method for preparing the same
#20CHIP PACKAGE WITH INTEGRATED OFF-DIE INDUCTOR
#21Integrated Circuit Packages and Methods of Forming the Same
#22SEMICONDUCTOR PACKAGE WITH EXPOSED ELECTRICAL CONTACTS
#23DOUBLE-SIDED HEAT DISSIPATION POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME
#24Electrical interconnect structure using metal bridges to interconnect die
#25COPPER INTERCONNECTS WITH SELF-ALIGNED HOURGLASS-SHAPED METAL CAP
#26METHOD FOR CREATING A DOCUMENT STRUCTURE, AND DOCUMENT STRUCTURE
#27Package and package-on-package structure having elliptical columns and ellipsoid joint terminals
#28Light emitting diode display with redundancy scheme
#29SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
#30Die and package structure
#31Chip-on-lead semiconductor device, and corresponding method of manufacturing chip-on-lead semiconductor devices
#32Display device and method for manufacturing display device
#33Manufacturing method of semiconductor structure
#34Semiconductor package
#35Light emitting diode display with redundancy scheme
#36Multi-die package with bridge layer
#37Stacked integrated circuits with redistribution lines
#38Semiconductor structure
#39Package and package-on-package structure having elliptical columns and ellipsoid joint terminals
#40Package structure and method of manufacturing the same
#41Light emitting diode display with redundancy scheme
#42Semiconductor Devices and Methods of Manufacture Thereof
#43Stacked integrated circuits with redistribution lines
#44Package structure and method of manufacturing the same
#45Semiconductor structure
#46Method for forming chip package structure
#47Semiconductor device package with a conductive post
#48Chip package structure including redistribution structure and conductive shielding film
#49Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance
#50Redistribution layers in semiconductor packages and methods of forming same
#51Light emitting diode display with redundancy scheme
#52Method of manufacturing semiconductor devices having conductive plugs with varying widths
#53Semiconductor device with a conductive post
#54Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
#55Methods for making multi-die package with bridge layer
#56Stacked integrated circuits with redistribution lines
#57Light emitting device
#58Semiconductor package with high routing density patch
#59Multi-die package with bridge layer and method for making the same
#60Fan out package structure and methods of forming
#61Light emitting diode display with redundancy scheme
#62Light emitting device
#63Method for manufacturing electronic devices
#64Method of fabricating a light emitting diode display with integrated defect detection test
#65Three-dimensional structure in which wiring is provided on its surface
#66Three-dimensional structure for wiring formation
#67Discrete device mounted on substrate
#68Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
#69Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
#70Method and apparatus for assembling electric components on a flexible substrate as well as assembly of an electric component with a flexible substrate
#71Microelectronic assembly tolerant to misplacement of microelectronic elements therein
#72Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
#73Multi-chip semiconductor package and method of fabricating the same
#74Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
#75Composite layered chip package
#76Layered chip package and method of manufacturing same
#77Layered chip package and method of manufacturing same
#78Semiconductor package structure and manufacturing method thereof
#79Semiconductor device package
#80Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance
#81Package unit and stacking structure thereof
#82Chip assembly having via interconnects joined by plating
#83Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
#84Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
#85Electronic package with stacked semiconductor chips
#86Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
#87Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
#88Semiconductor device
#89Method for metalizing blind vias
#90Manufacturing method of semiconductor device
#91UNIFIED SCALABLE HIGH SPEED INTERCONNECTS TECHNOLOGIES
#92Method of fabricating a semiconductor device
#93Semiconductor structure
#94Wafer-level fan-out wirebond packages