ClassID:

210113

H01L2224/49105 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Wire connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors; Disposition Connecting at different heights

Recent Application in this class:
#1
20250286006
2025-09-11

SEMICONDUCTOR PACKAGE INCLUDING AN ENCAPSULANT

#2
20240203930
2024-06-20

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

#3
20240030190
2024-01-25

SEMICONDUCTOR STACK STRUCTURE

#4
20230083493
2023-03-16

SEMICONDUCTOR PACKAGE INCLUDING AN ENCAPSULANT

#5
20220375891
2022-11-24

Package-on-package assembly with wire bonds to encapsulation surface

#6
20220302008
2022-09-22

Semiconductor device package

#7
20220037285
2022-02-03

MULTI-CHIP PACKAGE

#8
20210050322
2021-02-18

Package-on-package assembly with wire bonds to encapsulation surface

#9
20200168579
2020-05-28

Package-on-package assembly with wire bonds to encapsulation surface

#10
20190067539
2019-02-28

Semiconductor light emitting element package including solder bump

#11
20180350766
2018-12-06

Package-on-package assembly with wire bonds to encapsulation surface

#12
20180005974
2018-01-04

Semiconductor device including interconnected package on package

#13
20170358564
2017-12-14

Semiconductor package

#14
20170317070
2017-11-02

Apparatuses for communication systems transceiver interfaces

#15
20170317015
2017-11-02

Power module package having patterned insulation metal substrate

#16
20170287733
2017-10-05

Package-on-package assembly with wire bonds to encapsulation surface

#17
20170162403
2017-06-08

Method for fabricating stack die package

#18
20160268229
2016-09-15

Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller

#19
20160211237
2016-07-21

Package-on-package assembly with wire bonds to encapsulation surface

#20
20150287724
2015-10-08

Semiconductor device with output circuit and pad arrangements

#21
20150108579
2015-04-23

Semiconductor devices with output circuit and pad

#22
20150091118
2015-04-02

Package-on-package assembly with wire bonds to encapsulation surface

#23
20140273344
2014-09-18

Method for fabricating stack die package

#24
20100171177
2010-07-08

Semiconductor device with output circuit arrangement

#25
20090050940
2009-02-26

Semiconductor device

#26
20070120258
2007-05-31

Semiconductor device