210911 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding Combinations of bonding methods provided for in at least two different groups from -
Sub-classes:THREE DIMENSIONAL (3D) CHIPLET AND METHODS FOR FORMING THE SAME
#2SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME
#33D TRENCH CAPACITOR FOR INTEGRATED PASSIVE DEVICES
#4DIRECT HYBRID BOND PAD HAVING TAPERED SIDEWALL
#5ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES
#63D TRENCH CAPACITOR FOR INTEGRATED PASSIVE DEVICES
#7THREE DIMENSIONAL (3D) CHIPLET AND METHODS FOR FORMING THE SAME
#8METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
#9GANG-FLIPPING OF DIES PRIOR TO BONDING
#10Semiconductor Package and Method of Forming Same
#11Semiconductor device and method of manufacture
#12DIRECT BONDING METHODS AND STRUCTURES
#13Semiconductor device and method of manufacturing
#14BONDING ALIGNMENT MARKS AT BONDING INTERFACE
#153D trench capacitor for integrated passive devices
#16Semiconductor devices having adjoined via structures formed by bonding and methods for forming the same
#173D trench capacitor for integrated passive devices
#18Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same
#19Semiconductor devices having adjoined via structures formed by bonding and methods for forming the same
#20Bonding alignment marks at bonding interface
#21Semiconductor device and method of manufacturing
#22Semiconductor device and method of manufacture
#23Multi-chip package with offset 3D structure
#24Bonding alignment marks at bonding in interface
#25Semiconductor device packaging structure having through interposer vias and through substrate vias
#26Serializer-deserializer die for high speed signal interconnect
#27Multi-chip package with offset 3D structure
#28Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
#29Hybrid wafer-to-wafer bonding and methods of surface preparation for wafers comprising an aluminum metalization
#30Semiconductor device and method of manufacturing
#31Seal ring for bonded dies
#323D chip sharing clock interconnect layer
#33Method for forming hybrid bonding with through substrate via (TSV)
#34Bonded processed semiconductor structures and carriers
#35Hybrid bonding with through substrate via (TSV)
#36Bonded processed semiconductor structures and carriers
#37Treatment, before the bonding of a mixed Cu-oxide surface, by a plasma containing nitrogen and hydrogen
#38Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
#39ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS