Patents-Review.com
ClassID:

210950 ⎘

H01L2224/81026 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector; Pre-treatment of the bump connector or the bonding area Applying a precursor material to the bonding area

Recent Application in this class:
#1
20240312954
2024-09-19

STRUCTURES FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

 #2
20230335531
2023-10-19

Structures for low temperature bonding using nanoparticles

 #3
20230132060
2023-04-27

Methods for low temperature bonding using nanoparticles

 #4
20220149003
2022-05-12

FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES

 #5
20210225801
2021-07-22

Structures and methods for low temperature bonding using nanoparticles

 #6
20200243499
2020-07-30

Semiconductor memory device and method of manufacturing the same

 #7
20200152598
2020-05-14

Structures and methods for low temperature bonding using nanoparticles

 #8
20200098723
2020-03-26

Non-porous copper to copper interconnect

 #9
20190123027
2019-04-25

Package-on-package (PoP) structure including stud bulbs

 #10
20190109084
2019-04-11

Chip packages with sintered interconnects formed out of pads

 #11
20190067239
2019-02-28

Non-porous copper to copper interconnect

 #12
20180218998
2018-08-02

Structures and methods for low temperature bonding using nanoparticles

 #13
20180082969
2018-03-22

Chip alignment utilizing superomniphobic surface treatment of silicon die

 #14
20180047709
2018-02-15

Package-on-package (PoP) structure including stud bulbs

 #15
20170278817
2017-09-28

Chip alignment utilizing superomniphobic surface treatment of silicon die

 #16
20170170101
2017-06-15

Flip-chip on leadframe having partially etched landing sites

 #17
20170047307
2017-02-16

Structures and methods for low temperature bonding using nanoparticles

 #18
20170025391
2017-01-26

Package on-package (PoP) structure including stud bulbs

 #19
20160163672
2016-06-09

Dual-side reinforcement flux for encapsulation

 #20
20160155667
2016-06-02

Organic thin film passivation of metal interconnections

 #21
20150243624
2015-08-27

Microelectronic packages with nanoparticle joining

 #22
20150132889
2015-05-14

Package on-Package (PoP) structure including stud bulbs and method

 #23
20130134588
2013-05-30

Package-on-package (PoP) structure including stud bulbs and method

 #24
20130099380
2013-04-25

WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF

 #25
20120329182
2012-12-27

SEMICONDUCTOR DEVICE MOUNTING METHOD

 #26
20120067628
2012-03-22

Printed wiring board

 #27
20120025365
2012-02-02

Microelectronic packages with nanoparticle joining

 #28
20110297425
2011-12-08

WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF

 #29
20090065243
2009-03-12

Printed wiring board

 #30
20090026615
2009-01-29

Semiconductor device having external connection terminals and method of manufacturing the same

 #31
20080188040
2008-08-07

Method of manufacturing semiconductor device

 #32
20070105459
2007-05-10

Joining method and joining device

 #33
20050280130
2005-12-22

Printed wiring board

 #34
20050199989
2005-09-15

Semiconductor device and manufacturing method thereof