H01L2224/818 - CPC Classification Index

ClassID:

211054 ⎘

H01L2224/818 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector Bonding techniques

Sub-classes:

H01L2224/81801 » Soldering or alloying 2,3K
H01L2224/8184 » Sintering 74
H01L2224/8185 » using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester 103
H01L2224/8189 » using an inorganic non metallic glass type adhesive, e.g. solder glass 2
H01L2224/81893 » Anodic bonding, i.e. bonding by applying a voltage across the interface in order to induce ions migration leading to an irreversible chemical bond 9
H01L2224/81894 » Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces 160
H01L2224/81897 » Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like 31

Recent Application in this class:

20250266363

2025-08-21

ARCHITECTURE FOR COMPUTING SYSTEM PACKAGE

20250112154

2025-04-03

Power, Signaling and Thermal Path Co-optimization

20240355746

2024-10-24

ARCHITECTURE FOR COMPUTING SYSTEM PACKAGE

20240153908

2024-05-09

DRIVING SUBSTRATE, MICRO LED TRANSFER DEVICE AND MICRO LED TRANSFER METHOD

20240038669

2024-02-01

Architecture for computing system package

20230005878

2023-01-05

Temporary Chip Assembly, Display Panel, and Manufacturing Methods of Temporary Chip Assembly and Display Panel

20220223530

2022-07-14

Architecture for computing system package

20200126951

2020-04-23

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

20180286826

2018-10-04

Methods of interconnect for high density 2.5D and 3D integration

#10

20180182733

2018-06-28

Systems and methods for bonding semiconductor elements

#11

20180166416

2018-06-14

Method for transferring and placing a semiconductor device on a substrate

#12

20180082982

2018-03-22

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

#13

20180012877

2018-01-11

Communicating optical signals between stacked dies

#14

20170025398

2017-01-26

Die-die stacking

#15

20170012081

2017-01-12

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

#16

20160254252

2016-09-01

Systems and methods for bonding semiconductor elements

#17

20160172324

2016-06-16

Alignment of three dimensional integrated circuit components

#18

20160172252

2016-06-16

Alignment of three dimensional integrated circuit components

#19

20160099228

2016-04-07

Semiconductor device with at least one voltage-guided conductive filament

#20

20160071824

2016-03-10

Semiconductor package and method of manufacturing the same

#21

20160035696

2016-02-04

Method for forming package structure

#22

20150348951

2015-12-03

Systems and methods for bonding semiconductor elements

#23

20150228591

2015-08-13

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

#24

20150221602

2015-08-06

Flip-chip hybridisation of two microelectronic components using a UV anneal

#25

20150137366

2015-05-21

REACTIVE BONDING OF A FLIP CHIP PACKAGE

#26

20150097285

2015-04-09

Systems and methods for bonding semiconductor elements

#27

20140374145

2014-12-25

HERMETICALLY-SEALED ELECTRICAL CIRCUIT APPARATUS

#28

20140361429

2014-12-11

Semiconductor device with bumps and display device module incorporating the same

#29

20140342504

2014-11-20

Method of manufacturing an electronic device, and electronic device manufacturing apparatus

#30

20140227831

2014-08-14

Front side copper post joint structure for temporary bond in TSV application

#31

20130320529

2013-12-05

Reactive bonding of a flip chip package

#32

20130187293

2013-07-25

Electronic device having electrodes bonded with each other

#33

20120311855

2012-12-13

Apparatus for restricting moisture ingress

#34

20120064670

2012-03-15

Apparatus for restricting moisture ingress

#35

20120056320

2012-03-08

Semiconductor device and manufacturing method of semiconductor device

#36

20110049706

2011-03-03

Front side copper post joint structure for temporary bond in TSV application

#37

20100320596

2010-12-23

Method for fabricating a semiconductor package

#38

20100315110

2010-12-16

Hermeticity testing

#39

20100314733

2010-12-16

Apparatus for restricting moisture ingress

#40

20100314726

2010-12-16

Faraday cage for circuitry using substrates

#41

20100314149

2010-12-16

HERMETICALLY-SEALED ELECTRICAL CIRCUIT APPARATUS

#42

20100148376

2010-06-17

Flip chip mounting process and flip chip assembly

#43

20100129961

2010-05-27

MULTI CHIP STACKING WITH RELIABLE JOINING

#44

20080017995

2008-01-24

Flip chip mounting process and flip chip assembly

#45

20070001313

2007-01-04

Method of interconnecting terminals and method of mounting semiconductor devices

#46

20050199989

2005-09-15

Semiconductor device and manufacturing method thereof