Memory arrays and methods used in forming a memory array comprising strings of memory cells

Transistors including two-dimensional materials

Layout of static random access memory periphery circuit

Semiconductor device package and method of manufacturing the same

Semiconductor package

BARRIER MATERIALS BETWEEN BUMPS AND PADS

Methods for reducing dual damascene distortion

Integrated circuit device and method of manufacturing the same

Semiconductor device and oscillator

Multifunctional molecules for selective polymer formation on conductive surfaces and structures resulting therefrom

Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same

Graphene enabled selective barrier layer formation

Semiconductor devices and methods of forming the same

Interconnect structures with low-aspect-ratio contact vias

Semiconductor structure and manufacturing method thereof

Semiconductor package and semiconductor device

Semiconductor chip including low-k dielectric layer

Interconnect device and method

Semiconductor structure and manufacturing method thereof

Sensor package and method

Barrier-Less Structures

Semiconductor device and fabrication method thereof

Semiconductor device with air spacer and method for preparing the same

Capacitor device and manufacturing method therefor

Semiconductor device with air gap structure and method for preparing the same

Integrated assemblies comprising vertically-stacked decks

Semiconductor package including stacked semiconductor chips

Pad structure and manufacturing method thereof in semiconductor device

Semiconductor device and method for forming the same

Prevention of contact bottom void in semiconductor fabrication

Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects

Interconnect structure having fully aligned vias

Self-aligned top via scheme

Metal contact structure and method of forming the same in a semiconductor device

FinFET device with contact over dielectric gate

Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric

Semiconductor circuit with metal structure and manufacturing method

Three-dimensional vertical NOR flash thin-film transistor strings

Vertical memory devices and methods of manufacturing the same

Interconnect structure of three-dimensional memory device

Die stacks and methods forming same

Package structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Vertical semiconductor devices

Method of testing wafer

Helmet structures for semiconductor interconnects

Semiconductor device, package structure including a heat dissipation element having a conductive base and a plurality of antenna patterns and method of fabricating the semiconductor device

Semiconductor interconnect structure with double conductors

Semiconductor apparatus and equipment

Semiconductor device

Vertical interconnect elevator based on through silicon vias

Semiconductor device including via and wiring

Semiconductor device and method for manufacturing same

Semiconductor device

Dual metal silicide structures for advanced integrated circuit structure fabrication

Semiconductor structure and formation method thereof

Top via interconnects with wrap around liner

MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION

Semiconductor structure having air gap dielectric and the method of preparing the same

COMPOSITION FOR COBALT PLATING COMPRISING ADDITIVE FOR VOID-FREE SUBMICRON FEATURE FILLING

Antenna package structure and antenna packaging method

Tape, encapsulating process and optical device

Interconnect layout for semiconductor device

Memory device and semiconductor die, and method of fabricating memory device

Nonvolatile memory device having a vertical structure and a memory system including the same

Three-dimensional semiconductor device

Three-dimensional semiconductor memory device

Nonvolatile memory device and method for fabricating the same

Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same

Vertical memory devices

Microelectronic packages with high integration microelectronic dice stack

Package structure and assembly structure

Adhesive bonding composition and electronic components prepared from the same

Electronic apparatus and manufacturing method thereof

Integrated circuit device with through interconnect via and methods of manufacturing the same

Adjustable via dimension and chamfer angle

Semiconductor device

Wiring structure having an intermediate layer between an upper conductive structure and conductive structure

Semiconductor package

Methods for forming self-aligned interconnect structures

Interconnect structure having an etch stop layer over conductive lines

Memory cell with top electrode via

Capacitor Structure

Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection

Multi-die package structures including redistribution layers

Semiconductor device with guard ring

Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same

Integrated circuit having a high cell density

Interconnect and memory structures formed in the BEOL

Method of forming a multi-level interconnect structure in a semiconductor device

Semiconductor device and method of manufacturing the same

Semiconductor memory device and manufacturing method of the semiconductor memory device

Semiconductor device and method for fabricating the same

Semiconductor device and method for fabricating the same

Semiconductor memory device

Method, apparatus and system for wide metal line for SADP routing

Magnetic memory cell

Three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device

Three-dimensional semiconductor devices

Semiconductor memory device and manufacturing method thereof

Semiconductor memory device

Semiconductor structure and method for manufacturing the same

Package structure, chip structure and method of fabricating the same

Coupled line structures for wideband applications

Semiconductor structure and fabrication method thereof

Random cut patterning

Methods and apparatus for forming dual metal interconnects

Dual-gate trench IGBT with buried floating P-type shield

Self-aligned contacts in three-dimensional memory devices and methods for forming the same

Metallization layer formation process

Semiconductor structure and manufacturing method thereof

Semiconductor devices including contact plugs

Integrated circuit having a single damascene wiring network

Method of forming semiconductor device having a dual material redistribution line and semiconductor device

Fin field effect transistor (FinFET) device structure with interconnect structure

3D semiconductor device and structure

Power amplifier with shielded transmission lines

Semiconductor structure and associated fabricating method

Plugs for interconnect lines for advanced integrated circuit structure fabrication

High density capacitor implemented using FinFET

Semiconductor device

Semiconductor structure

Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof

Standard cell and an integrated circuit including the same

Interconnect structures having lines and vias comprising different conductive materials

Etch stop layer-based approaches for conductive via fabrication and structures resulting therefrom

Semiconductor device and method of manufacturing a semiconductor device

Semiconductor device with elongated pattern

Method for manufacturing an interconnect structure having a selectively formed bottom via

Integrated circuit package and method

Three-dimensional logic circuit

Magnetoresistive random access memory device and method of manufacturing the same

Semiconductor devices

Three-dimensional semiconductor memory device

Memory cell structure of a three-dimensional memory device

Semiconductor storage device

Semiconductor package

Chip package structure

Semiconductor device

Semiconductor device

Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure

Integrated circuit device and method of manufacturing the same

Semiconductor device with through-substrate via and its method of manufacture

Interconnect structure and manufacturing method for the same

Semiconductor device including a passivation spacer and method of fabricating the same

Method of designing semiconductor device

Pad limited configurable logic device

Si-based CTE-matched substrate for laser diode packaging

Semiconductor device including a plug

Three-dimensional semiconductor memory device and method of fabricating the same

Integrated circuit device

Staircase formation in three-dimensional memory device

SEMICONDUCTOR DEVICES

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

Semiconductor device

Package structure

Chip package structure

Semiconductor package including frame in which semiconductor chip is embedded

Integrated circuit layout, integrated circuit, and method for fabricating the same

Method of fabricating semiconductor device including dummy via anchored to dummy metal layer

Component inter-digitated vias and leads

Variable pitch and stack height for high performance interconnects

Sidewall interconnect metallization structures for integrated circuit devices

Wiring substrate and manufacturing method thereof

Back end of line via to metal line margin improvement

Sideways vias in isolation areas to contact interior layers in stacked devices

Semiconductor die with conversion coating

MEMORY DEVICES WITH A LOGIC REGION BETWEEN MEMORY REGIONS

Staggered lines for interconnect performance improvement and processes for forming such

Intermediate separation layers at the back-end-of-line

SUBSTRATE FOR AN ELECTRONIC DEVICE

Two-dimensional (2D) self-aligned contact (or via) to enable further device scaling

Semiconductor device and a method of manufacturing the same

Interconnect structure and method of forming the same

Semiconductor device having opening and via hole and method for manufacturing the same

Semiconductor structure

Photonic integrated package and method forming same

TSV testing method and apparatus

Memory cell with top electrode via

Capacitor structure and semiconductor structure

Method and structure for dual sheet resistance trimmable thin film resistors

Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same

Three-dimensional flash memory device including channel structures having enlarged portions

Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same

Anti-fuse cell and chip having anti-fuse cells

Tie off device

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

Methods of forming substrate interconnect structures for enhanced thin seed conduction

Multi-package assemblies having foam structures for warpage control

INTEGRATED CIRCUIT STRUCTURE

Method for forming titanium nitride barrier with small surface grains in interconnects

Method for forming semiconductor device structure with conductive line

Semiconductor device having a stacked structure

Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same

Connection of several circuits of an electronic chip

Semiconductor devices

Semiconductor structure with doped via plug

Self-aligned cut process for self-aligned via process window

Copper interconnect structure with manganese barrier layer

Method for forming lead wires in hybrid-bonded semiconductor devices

High current integrated circuit-based transformer

Semiconductor device

Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure

Three-dimensional memory device with support structures in slit structures and method for forming the same

SRAM cell and logic cell design

Neuromorphic computing device

Bonded die assembly containing a manganese-containing oxide bonding layer and methods for making the same

Hybrid integrated circuit package and method

Semiconductor device with die bumps aligned with substrate balls

Passivation scheme for pad openings and trenches

Semiconductor device and manufacturing method thereof

Semiconductor device, associated method and layout

Localized high density substrate routing

Semiconductor device and fabrication method for the same

Integrated circuit device with bonding structure and method of forming the same

Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device

Large via buffer

Integrated circuit structure of capacitive device

Semiconductor structure and method for manufacturing the same

Method for forming a semiconductor device structure having an electrical connection structure

Semiconductor structure and fabrication method thereof

Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication

Replacement gate structures for advanced integrated circuit structure fabrication

Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

Staircase and contact structures for three-dimensional memory

Three-dimensional semiconductor memory devices

Semiconductor device package with stress buffering layer and method for manufacturing the same

Semiconductor devices comprising planar waveguide transmission lines

Pseudo-stripline using double solder-resist structure

Chemical direct pattern plating method

MULTI-LAYER INDUCTOR

Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Metal via structure

Semiconductor memory device

Local interconnect with air gap

Lids for integrated circuit packages with solder thermal interface materials

Selective removal process to create high aspect ratio fully self-aligned via

Semiconductor device structures

Surface modified dielectric refill structure

Vias with multiconnection via structures

Drain and/or gate interconnect and finger structure

Shield structure for backside through substrate vias (TSVs)

Semiconductor structure and method of forming the same

Semiconductor memory device

Floating gate test structure for embedded memory device

Inverter cell structure and forming method thereof

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Integrated circuit package and method

Tri-layer CoWoS structure

COWOS structures and methods forming same

Semiconductor package for wafer level packaging and manufacturing method thereof

Air channel formation in packaging process

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

IC with thin film resistor with metal walls

Package structure and package-on-package structure

Semiconductor structure and method of fabricating wiring structure

Hermetic barrier for semiconductor device

Metallization interconnect structure formation

Semiconductor device with through silicon via structure

Integrated circuit packages with asymmetric adhesion material regions

Electronic device comprising an electronic chip mounted on top of a support substrate

Integrated circuit package and method

Semiconductor device and method for manufacturing the same

Interconnection element and method of manufacturing the same

Method and structure of metal cut

Semiconductor device structure having protection caps on conductive lines

Coaxial contacts for 3D logic and memory

Semiconductor memory device and production method thereof

Semiconductor device

Semiconductor package

Seal ring for hybrid-bond

Power distribution network using buried power rail

Applications of buried power rails

Semiconductor device and method of manufacturing the same

Integrated circuit structures with contoured interconnects

Interconnect hub for dies

Integrated-circuit devices and circuitry comprising the same

Semiconductor packages having thermal through vias (TTV)

Semiconductor device and method of manufacturing a semiconductor device

Self-aligned contacts for 3D logic and memory

Method to repair edge placement errors in a semiconductor device

Interconnects with tight pitch and reduced resistance

Metal interconnect structure and method for fabricating the same

Interconnect structure

Semiconductor device with embedded magnetic flux concentrator

Air gap type semiconductor device package structure and fabrication method thereof

Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof

Three-dimensional cross-point memory device containing inter-level connection structures and method of making the same

Integrated circuit device and method of fabricating the same

Three-dimensional semiconductor memory device

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Semiconductor integrated circuit device

Semiconductor structure and method for manufacturing a plurality thereof

3D integrated circuit

Density-graded adhesion layer for conductors

Method of forming stacked trench contacts and structures formed thereby

Semiconductor device

Multi-dimensional vertical switching connections for connecting circuit elements

LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM