Word line structure of three-dimensional memory device

Three dimensional semiconductor device and method of forming the same

Memory cell structure of a three-dimensional memory device

Semiconductor device and method of manufacturing the same

Through silicon via design for stacking integrated circuits

Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same

Semiconductor die

Integrated assemblies having capacitive units, and having resistive structures coupled with the capacitive units

Package structure

Semiconductor device, circuit board structure and manufacturing method thereof

Semiconductor device bonded by bonding pads

Vertical memory devices including stacked conductive lines and methods of manufacturing the same

Via for semiconductor device connection and methods of forming the same

Package structure and manufacturing method thereof

Slit oxide and via formation techniques

METHODS, DEVICES, AND SYSTEMS FOR SUBSTRATE TEMPERATURE MEASUREMENTS

Interconnect with self-forming wrap-all-around barrier layer

Microelectronic assembly from processed substrate

Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom

Semiconductor device and manufacturing method thereof

Interconnect structure and method for forming the same

Device packaging using a recyclable carrier substrate

Semiconductor device, method of generating layout diagram and system for same

Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same

Through-array conductive via structures for a three-dimensional memory device and methods of making the same

Semiconductor device including a capacitor structure and a thin film resistor and a method of fabricating the same

Semiconductor device

3D stacked memory and vertical interconnect structures for 3D stacked memory

Method and apparatus for reducing noise on integrated circuit using broken die seal

SEMICONDUCTOR DEVICES

IC structure with air gaps and protective layer and method for manufacturing the same

Semiconductor storage device

CTE-tuned pyrolytic graphite (PG) substrate to minimize joining stress between laser diode and the substrate

Three-dimensional semiconductor memory device including an electrode connecting portion

Three-dimensional semiconductor memory device and method of manufacturing the same

Crenellated charge storage structures for 3D NAND

Vertical semiconductor device

Fin patterning for advanced integrated circuit structure fabrication

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Multiple layer metal-insulator-metal (MIM) structure

Semiconductor memory device

Semiconductor package structure and a method of manufacturing the same

Methods of fabricating semiconductor devices

Interconnect Structure with Porous Low K Film

Constructing via meshes for high performance routing on silicon chips

Systems and methods for monitoring copper corrosion in an integrated circuit device

Antenna apparatus and method

Cell architecture based on multi-gate vertical field effect transistor

Method for forming staircase structure of three-dimensional memory device

Microelectronic packages with high integration microelectronic dice stack

Semiconductor package and method of manufacturing the same

Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating

Semiconductor structure and method for fabricating the same

Semiconductor device

Selectable vias for back end of line interconnects

Multi-layer substrate and method for manufacturing multi-layer substrate

THERMAL MANAGEMENT SOLUTIONS FOR INTEGRATED CIRCUIT ASSEMBLIES USING PHASE CHANGE MATERIALS

Method of forming self-aligned via

SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME

Chamferless interconnect vias of semiconductor devices

Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

Multi-tier co-placement for integrated circuitry

Power transistor with distributed gate

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

Semiconductor device and manufacturing method thereof

Semiconductor memory device and method for manufacturing same

Three-dimensional semiconductor memory device

Three-dimensional memory devices having through stair contacts and methods for forming the same

Semiconductor Package

Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression

Method of manufacturing via structures of semiconductor devices

Semiconductor package with improved interposer structure

High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations

MULTILAYER MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor device and a method of manufacturing the same

Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

Microelectronic assemblies having conductive structures with different thicknesses

Three-dimensional semiconductor memory devices

Memory device and electronic device including insulating patterns with different thermal conductivities

FERROELECTRICS USING THIN ALLOY OF PARA-ELECTRIC MATERIALS

Memory device having vertical structure

Electrostatic protection circuit, array substrate, display panel and display device

Fusion memory device and method of fabricating the same

Chip package structure with dummy bump and method for forming the same

Semiconductor device and method for fabricating the same

Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same

Devices including conductive interconnect structures, related electronic systems, and related methods

Method of forming a thermal shield in a monolithic 3-D integrated circuit

Superconducting device with multiple thermal sinks

Stair step structures including insulative materials, and related devices

Semiconductor device

Three-dimensional semiconductor memory devices

Three-dimensional semiconductor memory device

Multi-stack three-dimensional memory devices and methods for forming the same

Three-dimensional memory device containing etch stop structures and methods of making the same

Three-dimensional semiconductor memory devices

Semiconductor device

3D stacked integrated circuits having functional blocks configured to provide redundancy sites

Semiconductor device

Integrated circuits and methods for forming thin film crystal layers

Semiconductor device and manufacturing method thereof

Transistor with non-circular via connections in two orientations

Memory and fabrication method thereof

Semiconductor package

Thermal bump networks for integrated circuit device assemblies

Apparatus comprising staircase structures

METAL INTERCONNECTION AND FORMING METHOD THEREOF

Semiconductor packages configured for measuring contact resistances and methods of obtaining contact resistances of the semiconductor packages

Integrally-formed multiple-path power amplifier with on-die combining node structure

Staircase and contact structures for three-dimensional memory

Three-dimensional memory devices and fabricating methods thereof

Controlled resistance integrated snubber for power switching device

Integrated assemblies comprising vertically-stacked decks of memory arrays

Semiconductor structure and associated manufacturing method

Semiconductor devices having a conductive pillar and methods of manufacturing the same

Package on antenna package

System for layout design of structure with inter layer vias

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Integrated circuit package and method

Conductive via and metal line end fabrication and structures resulting therefrom

Methods of semiconductor device fabrication

Semiconductor device and method to fabricate the semiconductor device

System for generating standard cell layout having engineering change order (ECO) cells

Standard cell architecture for gate tie-off

Standard cell architecture for gate tie-off

Cap structure for trench capacitors

Three-dimensional vertical NOR flash thin-film transistor strings

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Redistribution layers in semiconductor packages and methods of forming same

MMICs with backside interconnects for fanout-style packaging

Semiconductor packages

Semiconductor packages

Semiconductor package

Methods of manufacturing semiconductor device and semiconductor device

Functional component within interconnect structure of semiconductor device and method of forming same

METAL FILAMENT VIAS FOR INTERCONNECT STRUCTURE

Semiconductor device and method of manufacture

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME

PACKAGE MODULE

Semiconductor device and manufacturing method thereof

Interconnect structure of semiconductor device including barrier layer located entirely in via

Semiconductor structure and fabrication thereof

Landing metal etch process for improved overlay control

Constructing via meshes for high performance routing on silicon chips

Integrated MIM diode

Three-dimensional memory device including replacement crystalline channels and methods of making the same

Semiconductor device having stacked field effect transistors

Method of manufacturing a semiconductor device

Semiconductor package

Bonding pad, semiconductor structure, and method of manufacturing semiconductor structure

Embedded reference layers for semiconductor package substrates

Semiconductor device with multi-layer dielectric

Manufacturing method of stacked multilayer structure

Semiconductor package

Semiconductor structure and manufacturing method thereof

Integrated circuit having heterogeneous gate contacts over active regions

Method and apparatus for nanoscale-dimension measurement using a diffraction pattern filter

Electrical connection for semiconductor devices

Semiconductor devices and methods of forming same

Vertical dispersive readout of qubits of a lattice surface code architecture

Thin film transistor and fabricating method thereof, array substrate and display device

Three-dimensional memory devices having through array contacts and methods for forming the same

Three-dimensional memory devices having through array contacts and methods for forming the same

Buried conductive layer supplying digital circuits

Integrated circuit with vertical structures on nodes of a grid

Semiconductor device

Semiconductor device, semiconductor package and method of manufacturing the same

Package module

Interconnect structure for semiconductor device and methods of fabrication thereof

Fan-out semiconductor package

Top electrode interconnect structures

Methods and apparatus for scribe seal structures

Semiconductor device having interconnection structure

Integration of air spacer with self-aligned contact in transistor

Structure and method for FinFET device with contact over dielectric gate

Formation of air gap spacers for reducing parasitic capacitance

Formation of air gap spacers for reducing parasitic capacitance

Formation of air gap spacers for reducing parasitic capacitance

Semiconductor device structure and method for forming the same

Through array contact structure of three- dimensional memory device

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Transistor with integrated capacitor

Distributed decoupling capacitor

Manufacturing method of package on package structure

System on integrated chips and methods of forming same

High aspect ratio connection for EMI shielding

GAN-based, lateral-conduction, electronic device with improved metallic layers layout

Integrated fan-out package with antenna components and manufacturing method thereof

FAN-OUT SEMICONDUCTOR PACKAGE

SYSTEM AND METHOD OF LAYING OUT CIRCUITS USING METAL OVERLAYS IN STANDARD CELL LIBRARY

PACKAGE STRUCTURE AND PACKAGING PROCESS

STACKED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Test structures connected with the lowest metallization levels in an interconnect structure

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Metallic interconnect structures with wrap around capping layers

Metallic interconnect structures with wrap around capping layers

Via connection to a partially filled trench

Stacked chip layout

RRAM devices with reduced forming voltage

Systems and methods for fabrication of superconducting integrated circuits

Integrated circuit devices including vertical field-effect transistors (VFETs)

Semiconductor device and method of forming patterns for a semiconductor device

LDMOS DEVICE WITH A DRAIN CONTACT STRUCTURE WITH REDUCED SIZE

Semiconductor circuit with metal structure having different pitches

Semiconductor device and method of manufacturing the same

Semiconductor device

Memory device with reduced-resistance interconnect

Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits

Integrated circuit devices including vertical field-effect transistors (VFETs)

Semiconductor device including vertical routing structure and method for manufacturing the same

Semiconductor device structure and method for manufacturing the same

Semiconductor package with first and second encapsulants

Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

Line structure and a method for producing the same

Line structure and a method for producing the same

Semiconductor package

Semiconductor device extension insulation

Back end of line metallization structure

Chip packaging structure and manufacturing method thereof

Back end of line metallization structure

Interconnect structure having metal layers enclosing a dielectric

Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory

Interconnect structure for fin-like field effect transistor

Field effect transistor devices with self-aligned source/drain contacts and gate contacts positioned over active transistors

Method of forming self-aligned via

Method and IC design with non-linear power rails

METAL INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING SAME

Method of forming barrier free contact for metal interconnects

Fence structure to prevent stiction in a MEMS motion sensor

Contact structure with insulating cap

Semiconductor device

Semiconductor arrangement and method of making

Semiconductor structure

Anti-fuse cell and chip having anti-fuse cells

DRAM circuitry, and integrated circuitry

Integrated circuit having vertical transistor and semiconductor device including the integrated circuit

Architecture for monolithic 3D integration of semiconductor devices

Semiconductor device including a field effect transistor

Package structure, die and method of manufacturing the same

Surface finishes with low rBTV for fine and mixed bump pitch architectures

Sidewall spacer to reduce bond pad necking and/or redistribution layer necking

Package structure and manufacturing method thereof

Semiconductor device and method of forming same

Customisation of an integrated circuit during the realisation thereof

Graphene layer for reduced contact resistance

Package structure, semiconductor package and method of fabricating the same

Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices

Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices

Via sizing for IR drop reduction

Semiconductor package

Integrated circuit including supervia and method of making

Plane-less voltage reference interconnects

Integration of artificial intelligence devices

Ion through-substrate via

Semiconductor device with self-aligned vias

Structure and method for forming fully-aligned trench with an up-via integration scheme

Cobalt interconnect structure including noble metal layer

Selective deposition for integrated circuit interconnect structures

Semiconductor device and method for making the same

Semiconductor device and method of forming the same

Semiconductor device and methods of manufacturing thereof

Method for forming pattern and manufacturing method of package

Semiconductor device with filler cell region, method of generating layout diagram and system for same

Integrated circuit and method of manufacturing the same

SEMICONDUCTOR DEVICE

Semiconductor device including conductive structure and manufacturing method thereof

Techniques for MRAM top electrode via connection

Semiconductor device and method of fabricating the same

Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same

Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same

Three-dimensional memory devices and fabricating methods thereof

Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices

Standard cell for removing routing interference between adjacent pins and device including the same

Integrated circuit and method of generating integrated circuit layout

3D packages and methods for forming the same

Semiconductor packages including a supporting block supporting an upper chip stack

Interconnect structure with vias extending through multiple dielectric layers

Interconnection structure and methods of fabrication the same

Method of preventing pattern collapse

On-die termination (ODT) circuit configurable with via layer to support multiple standards

Semiconductor device with damascene structure

Vertical memory device including common source line structure

Semiconductor devices having electrically and optically conductive vias, and associated systems and methods

Interconnect structures

Method of fabricating a memory device having multiple metal interconnect lines

Semiconductor memory device with 3D structure

Low cost metallization during fabrication of an integrated circuit (IC)

Cell having stacked pick-up region

Semiconductor devices including contact plugs

Vias for cobalt-based interconnects and methods of fabrication thereof

Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom

Airgap vias in electrical interconnects

Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

Semiconductor devices

Semiconductor device

Flash memory structure with reduced dimension of gate structure and methods of forming thereof

Semiconductor device

Electronic device

Buffer layer(s) on a stacked structure having a via