Semiconductor structure and method of forming

Advanced crack stop structure

Contact structure and formation thereof

Method for forming semiconductor device structure with conductive line

Semiconductor memory device

Semiconductor devices

Semiconductor structure

Method of forming graphene and metallic cap and barrier layers for interconnects

Via structure and methods thereof

Transistor with non-circular via connections in two orientations

Devices including stair step structures adjacent substantially planar, vertically extending surfaces of a stack structure

Fan-out package structure and method of manufacturing the same

Carrier for chip packaging and manufacturing method thereof

Interconnection structure and manufacturing method thereof

Controlling performance and reliability of conductive regions in a metallization network

Controlling performance and reliability of conductive regions in a metallization network

Semiconductor device for sensing impedance changes in a medium

Thin-film variable metal-oxide-semiconductor (MOS) capacitor for passive-on-glass (POG) tunable capacitor

Resistive memory

Nonvolatile memory device and method for fabricating the same

Semiconductor memory

Interconnect structure and method of forming same

Semiconductor package

Semiconductor device and manufacturing method thereof

Method for forming semiconductor contact structure

Semiconductor package, package-on-package device, and method of fabricating the same

Chip package

Skip via for metal interconnects

Logic drive based on multichip package using interconnection bridge

Systems and methods to enhance passivation integrity

Contact over active gate structures for advanced integrated circuit structure fabrication

Stacked self-aligned transistors with single workfunction metal

Semiconductor structure and manufacturing method for the same

Array substrate and manufacturing method therefor, display panel, and display device

Semiconductor device and manufacturing method of the semiconductor device

Vertical memory devices

Peripheral circuitry under array memory device and method of fabricating thereof

Strap-cell architecture for embedded memory

Vertical transistor contact for a memory cell with increased density

Semiconductor structure

Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture

Semiconductor device with multiple polarity groups

Semiconductor devices and manufacturing methods of the same

Metal bumps and method forming same

OPEN PAD STRUCTURE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

Mutli-chip package with encapsulated conductor via

Semiconductor package having mark with identification information

Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same

Microelectronic device including non-homogeneous build-up dielectric

DESIGN AND PROCESS FOR A PRECISION RESISTOR

Vias with metal caps for underlying conductive lines

Interconnect structure and related methods

Semiconductor device and method of fabricating the same

Semiconductor package

Semiconductor devices and methods of manufacturing the same

Integrated circuit package and method

Single mask lithography line end enhancement

Microelectronic assemblies having an integrated voltage regulator chiplet

Method for manufacturing semiconductor device with through silicon via structure

Sensor package and method

Integrated circuit package and method

Semiconductor structure with polyimide packaging and manufacturing method

SEMICONDUCTOR DEVICE AND METHOD

Semiconductor structure having a repaired dielectric layer

Fin field-effect transistor device and method of forming the same

Structure and method for interconnection with self-alignment

Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same

Conductive interconnect structures in integrated circuits

Selective deposition of metal barrier in damascene processes

Collar formation for chamfer-less and chamfered vias

Conformal low temperature hermetic dielectric diffusion barriers

Layer for side wall passivation

Semiconductor device including a blocking pattern in an interconnection line

Semiconductor device and manufacturing method thereof

Fan-out packages and methods of forming the same

Method and system for manufacturing a semiconductor device

Techniques for MRAM MTJ top electrode connection

Method to improve HKMG contact resistance

Control gate strap layout to improve a word line etch process window

Semiconductor device

Capacitor device and manufacturing method therefor

On-die capacitor for a VLSI chip with backside metal plates

Interconnect landing method for RRAM technology

Vertical memory device and method for fabricating the same

Three-dimensional flat NAND memory device including wavy word lines and method of making the same

Semiconductor memory device

Staircase structures for electrically connecting multiple horizontal conductive layers of a 3-dimensional memory device

Fin-based strap cell structure for improving memory performance

Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

Method for manufacturing monolithic three-dimensional (3D) integrated circuits

Semiconductor package

3DIC structure with protective structure and method of fabricating the same

Structures and methods for reducing thermal expansion mismatch during integrated circuit packaging

NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS

Semiconductor structure with high resistivity wafer and fabricating method of bonding the same

Self-aligned chamferless interconnect structures of semiconductor devices

Electrical fuse structure and method of formation

Interconnect structure for logic circuit

Methods of forming interconnect structures in semiconductor fabrication

TRANSISTOR, PACKAGED DEVICE, AND METHOD OF FABRICATION

Transistor with shield structure, packaged device, and method of fabrication

Semiconductor structure and manufacturing method thereof

Void-free high aspect ratio metal alloy interconnects and method of manufacture using a solvent-based etchant

Contacts and interconnect structures in field-effect transistors

Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices

Multi-dimensional integrated circuit having multiple planes and memory architecture having a honeycomb or bee hive structure

Composite and transistor

Scalable circuit-under-pad device topologies for lateral GaN power transistors

Memory device including a memory element between wiring layers and method of manufacturing memory device

Solid-state imaging device and electronic apparatus

Array substrate and manufacturing method thereof, display panel

Semiconductor device and method of manufacturing semiconductor device

Semiconductor memory device

One transistor and one ferroelectric capacitor memory cells in diagonal arrangements

Memory circuit layout method

Package structure and manufacturing method thereof

Pad structure and manufacturing method thereof in semiconductor device

Alignment mark design for packages

Three-dimensional semiconductor device

Semiconductor device and method for manufacturing the same

METALLIC CARBON QUANTUM WIRE FROM SELF-ASSEMBLED ALPHALTENE

Hybrid dielectric scheme for varying liner thickness and manganese concentration

Semiconductor devices, semiconductor packages and methods of forming the same

Method and apparatus for supplying power to VLSI silicon chips

Semiconductor device including gate pattern having pad region

Semiconductor device

Selective formation of conductor nanowires

Liner-free and partial liner-free contact/via structures

Redistribution substrate, method of fabricating the same, and semiconductor package including the same

SEMICONDUCTOR DEVICE

Stacked through-silicon vias for multi-device packages

Package structure and method for forming the same

PAD STRUCTURES IN SEMICONDUCTOR DEVICES

Semiconductor device with reduced via resistance

Semiconductor device with reduced via resistance

Method Of Forming Via With Embedded Barrier

Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability

Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability

Passivating silicide-based approaches for conductive via fabrication and structures resulting therefrom

Aluminum-containing layers and methods of forming the same

Self-aligned pattern formation for a semiconductor device

Ruthenium-containing semiconductor structure and method of manufacturing the same

Three-dimensional logic circuit

Back end of line metallization structures

Semiconductor device and method for fabricating the same

Contacts for highly scaled transistors

Capacitor having multiple graphene structures

Semiconductor device

Microelectronic devices, electronic systems, and related methods

Semiconductor package and method of fabricating the same

Connector formation methods and packaged semiconductor devices

Via rail solution for high power electromigration

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Impedance controlled electrical interconnection employing meta-materials

Logic cell structure and method

Selective deposition of embedded thin-film resistors for semiconductor packaging

Fan-out semiconductor package

Semiconductor devices including contacts and conductive line interfaces with contacting sidewalls

Via-based vertical capacitor and resistor structures

Fan-out semiconductor package

Single metallization scheme for gate, source, and drain contact integration

Self-aligned nanowire formation using double patterning

Middle of the line self-aligned direct pattern contacts

Integration of air spacer with self-aligned contact in transistor

Barrier layer formation for conductive feature

Barrier layer formation for conductive feature

METHOD OF FABRICATING INTERCONNECTION LINE OF SEMICONDUCTOR DEVICE

Interconnect structure and manufacturing method for the same

Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

Magnetoresistive memory cell and method for fabricating the same

Semiconductor device and method for fabricating the same

Substrate structure and manufacturing method thereof

Capacitor structure and method for manufacturing the same

Semiconductor structure and manufacturing method for the same

Image sensors

Semiconductor memory device and method of manufacturing semiconductor memory device

Semiconductor memory device

Semiconductor storage device

Integrated circuit including at least one memory cell with an antifuse device

Semiconductor device

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Multi-wafer stack structure and forming method thereof

Stack packages including bridge dies

Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics

Semiconductor device and method of forming the same

Radiofrequency device and manufacturing method thereof

Fan-out semiconductor package

Semiconductor package and method of manufacturing a semiconductor package

Semiconductor device with vertically separated openings and manufacturing method thereof

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor device

Semiconductor device and method for fabricating the same

Transistor shield structure, packaged device, and method of manufacture

Semiconductor device and method for manufacturing same

Semiconductor device and manufacturing method thereof

Semiconductor chips and methods of manufacturing the same

Metal gate structure cutting process

Semiconductor structure

Contact over active gate structure

Contact over active gate structure

Etching to reduce line wiggling

Low resistivity films containing molybdenum

Interconnection structure and method of forming the same

Plasma polymerized thin film having low dielectric constant, device, and method of preparing thin film

Pad limited configurable logic device

Closely packed vertical transistors with reduced contact resistance

INTEGRATED CIRCUIT DEVICE

MAGNETIC CORE INDUCTORS ON PACKAGE SUBSTRATES

Integrated circuit device and method for manufacturing same

Three-dimensional memory devices having through array contacts and methods for forming the same

Packaged semiconductor device

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Wiring with external terminal

Hyperchip

Wirebond and leadframe magnetic inductors

Guard ring for photonic integrated circuit die

Semiconductor device and method of manufacturing the same

MICROELECTRONIC DEVICES AND METHODS FOR ENHANCING INTERCONNECT RELIABILITY PERFORMANCE USING TUNGSTEN CONTAINING ADHESION LAYERS TO ENABLE COBALT INTERCONNECTS

Dual-mode wireless charging device

Package-integrated multi-turn coil embedded in a package magnetic core

Semiconductor devices employing a barrier layer

Method of forming a straight via profile with precise critical dimension control

Semiconductor chip, package structure, and pacakge-on-package structure

Structure and method of metal wraparound for low via resistance

Advanced lithography and self-assembled devices

Multi-layer embedded magnetic inductor coil

Single metallization scheme for gate, source, and drain contact integration

Controlling back-end-of-line dimensions of semiconductor devices

Semiconductor devices comprising conductive patterns of varying dimensions and related systems

Via cleaning to reduce resistance

Reducing contact resistance in vias for copper interconnects

Via structure with low resistivity and method for forming the same

Semiconductor memory device

Memory cell structure

Semiconductor structure

STRUCTURES AND METHODS FOR LARGE INTEGRATED CIRCUIT DIES

Semiconductor package including thermal relaxation block and manufacturing method thereof

Signal conductor routing configurations and techniques

Method and structure to construct cylindrical interconnects to reduce resistance

Method and structure to construct cylindrical interconnects to reduce resistance

Chip structure and method for forming the same

Semiconductor device including deep vias, and method of generating layout diagram for same

Method of forming a straight via profile with precise critical dimension control

Semiconductor structure

Semiconductor device and method of manufacturing the same

Differentiated molecular domains for selective hardmask fabrication and structures resulting therefrom

Metal interconnect structure and method for fabricating the same

Three-dimensional memory device including liner free molybdenum word lines and methods of making the same

Package structure

Advanced crack stop structure

Integrated circuit devices including a boron-containing insulating pattern

Fan-out semiconductor package

Metal line structure and method

CIRCUIT DEVICE PROVIDED WITH CIRCUIT BOARD AND CIRCUIT COMPONENT, AND METHOD FOR MANUFACTURING SAID CIRCUIT DEVICE

Semiconductor device

Semiconductor device with multi-layered wiring and method for fabricating the same

Semiconductor device and nonvolatile memory

High density embedded interconnects in substrate

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR PACKAGE

Heat dissipation substrate, manufacturing method thereof and chip package structure

Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Interconnect structure

Airgap formation in BEOL interconnect structure using sidewall image transfer

Semiconductor apparatus including uncrowned and crowned cells and method of making

Production method for multilayer wiring board

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

High power transistor with interior-fed gate fingers

Semiconductor memory device

Vertical transistors with different gate lengths

Vertical transistors with different gate lengths

Manufacturing method of semiconductor package

Package structures and methods for fabricating the same

SEMICONDUCTOR DEVICE

Three-dimensional integrated circuit structures

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES

Elongated pattern and formation thereof

Wafer chip scale packaging with ball attach before repassivation

Method of etching one or more of mixed metal and dielectric layers of a semiconductor device

Memory cell with top electrode via

Three-dimensional vertical NOR flash thin-film transistor strings

Three-dimensional memory device with corrosion-resistant composite spacer

SRAM cell and logic cell design

Through silicon via design for stacking integrated circuits

Metal zero contact via redundancy on output nodes and inset power rail architecture

POST CMP PROCESSING FOR HYBRID BONDING

Semiconductor package

Semiconductor device, manufacturing method, and electronic device

Method for protecting an integrated circuit, and corresponding device

Advanced crack stop structure

Advanced crack stop structure

Semiconductor device

Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure

Semiconductor package and antenna module including the same

Interconnect structure and electronic device employing the same

IC with thin film resistor with metal walls

Forming conductive plugs for memory device

Semiconductor package and method