Interconnect structures for integrated circuits and their formation

Methods for fabricating and forming semiconductor device structures including damascene structures

On-chip capacitors and methods of assembling same

Multi-level stack having multi-level contact and method

Semiconductor package with through silicon via interconnect and method for fabricating the same

Apparatuses including scalable drivers and methods

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Interconnect structure having smaller transition layer via

Ultrathin buried die module and method of manufacturing thereof

Bonding pad structure with dense via array

Interconnect structure and method for forming the same

Semiconductor package

PCB based RF-power package window frame

Element array with a plurality of electromechanical conversion devices

Thin film transistor array substrate

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

Adaptive patterning for panelized packaging

Adaptive patterning for panelized packaging

Semiconductor device

Through-silicon via with a non-continuous dielectric layer

Method of fabricating integrated optoelectronic interconnects with side mounted transducer

Plasma protection diode for a HEMT device

Processes for forming integrated circuits and integrated circuits formed thereby

Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability

Method of forming double pattern in a structure

Method for fabricating a physical unclonable interconnect function array

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Dual hard mask lithography process

Metal fuse structure for improved programming capability

Semiconductor device having non-planar interface between a plug layer and a contact layer

Semiconductor package including an organic substrate and interposer having through-semiconductor vias

Semiconductor structure having aluminum layer with high reflectivity

Stress reduction apparatus with an inverted cup-shaped layer

Semiconductor devices having through-vias and methods for fabricating the same

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device having groove-shaped via-hole

Meander line resistor structure

Semiconductor device including stacked semiconductor chips

Three dimensional structure memory

Microelectronic device having metal interconnection levels connected by programmable vias

Memory device

Semiconductor device including a first wiring having a bending portion a via

Microelectronic devices and methods for manufacturing microelectronic devices

Semiconductor devices with nonconductive vias

MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

Integrating through substrate vias into middle-of-line layers of integrated circuits

Back-end electrically programmable fuse

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Metal Layout of an Integrated Power Transistor and the Method Thereof

Semiconductor device including two groove-shaped patterns

Electrically conductive device and manufacturing method thereof

Structure and method for a transformer with magnetic features

Electrical fuse structure and method of fabricating same

Semiconductor device having groove-shaped via-hole

Strained transistor structure

Adaptive patterning for panelized packaging

Multilayer connection structure

Three-dimensional semiconductor devices

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

Semiconductor chip having plural penetration electrode penetrating therethrough

SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME

Interconnects for stacked non-volatile memory device and method

Semiconductor device and method for manufacturing the same

Semiconductor device and manufacturing method thereof

Systems and methods for stacked semiconductor memory devices

Trap rich layer with through-silicon-vias in semiconductor devices

Method of protecting against via failure and structure therefor

Multilayer interconnects with an extension part

Semiconductor device

Methods and apparatus to improve reliability of isolated vias

Redundant via structure for metal fuse applications

E-fuses containing at least one underlying tungsten contact for programming

Wiring structure in a semiconductor device, method of forming the wiring structure, semiconductor device including the wiring structure and method of manufacturing the semiconductor device

Semiconductor devices and methods of manufacturing the same

Barrier for through-silicon via

Semiconductor device

Low energy etch process for nitrogen-containing dielectric layer

Semiconductor device and method

IC scan cell coupled to TSV top and bottom contacts

Through substrate via structures and methods of forming the same

Semiconductor device with damascene bit line and method for fabricating the same

ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME

Three-dimensional vertically interconnected structure

Interconnect structure with an electromigration and stress migration enhancement liner

Process for forming package-on-package structures

HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE

Semiconductor device and method of manufacturing the same

Wafer level chip scale package and method of manufacturing the same

Semiconductor device and manufacturing method of the same

Package-on-package system with through vias and method of manufacture thereof

Power semiconductor module with integrated thick-film printed circuit board

Semiconductor device and method of manufacturing the same

Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

Semiconductor interconnect structure having enhanced performance and reliability

Rectangular via for ensuring via yield in the absence of via redundancy

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

Methods of forming semiconductor devices having capacitor and via contacts

Method for forming carbon nanotubes and carbon nanotube film forming apparatus

Package systems including passive electrical components

Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

Semiconductor device

Method for manufacturing semiconductor device using anisotropic etching

Semiconductor devices having through electrodes and methods of fabricating the same

INTEGRATED CIRCUIT INCLUDING FRONT SIDE AND BACK SIDE ELECTRICAL INTERCONNECTS

NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME

Bond pad structure to reduce bond pad corrosion

Methods of forming interconnects

Conductive routings in integrated circuits using under bump metallization

Multi-chip wafer level package

Trap rich layer with through-silicon-vias in semiconductor devices

Interconnecting mechanism for 3D integrated circuit

SEMICONDUCTOR DEVICE COMPRISING VARIABLE-SIZED CONTACT, METHOD OF FORMING SAME, AND APPARATUS COMPRISING SAME

Packaged microelectronic elements having blind vias for heat dissipation

Semiconductor device

MRAM with sidewall protection and method of fabrication

Via structure

Low stress vias

Photoactive compound gradient photoresist

CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE

Implementing integrated circuit mixed double density and high performance wire structure

Integrated thermoelectric generator

Composite semiconductor device with integrated diode

Semiconductor package and method of manufacturing the same

Stacked packages having through hole vias

SEMICONDUCTOR DEVICE

Package interconnects

INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME

Overlapping contacts for semiconductor device

Method and material for forming a double exposure lithography pattern

Via structure for integrated circuits

Method of manufacturing a semiconductor device and semiconductor device

Single exposure in multi-damascene process

Nanoscale interconnects fabricated by electrical field directed assembly of nanoelements

E-fuse structures and methods of manufacture

Semiconductor memory device and method for manufacturing same

Methods for via structure with improved reliability

Semiconductor structure formed by double patterning technique

Reliable packaging and interconnect structures

Semiconductor device having groove-shaped via-hole

Gap filling method for dual damascene process

Electromagnetic shield and associated methods

Semiconductor device having through silicon vias and manufacturing method thereof

Non-hierarchical metal layers for integrated circuits

Three-dimensional semiconductor memory devices having double cross point array and methods of fabricating the same

Conductive structures, systems and devices including conductive structures and related methods

Methods of forming through-substrate interconnects

Semiconductor integrated circuit with multi-cut via and automated layout method for the same

Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics

BEOL structures incorporating active devices and mechanical strength

BEOL compatible FET structrure

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, DISPLAY APPARATUS AND ELECTRONIC APPARATUS

Interposer test structures and methods

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

Copper-filled trench contact for transistor performance improvement

Semiconductor device and manufacturing method thereof

On-chip interconnects with reduced capacitance and method of afbrication

Bonding pad structure for a backside illuminated image sensor device and method of manufacturing the same

Wetting wave front control for reduced air entrapment during wafer entry into electroplating bath

EMBEDDED CAPACITOR DEVICE AND METHODS OF FABRICATION

Finger metal oxide metal capacitor structures

Semiconductor device

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Multilayer interconnect structure and method for integrated circuits

Semiconductor device having groove-shaped via-hole

System comprising a semiconductor device and structure

Semiconductor device having groove-shaped via-hole

Interconnects for stacked non-volatile memory device and method

Microelectronic devices with through-silicon vias and associated methods of manufacturing

Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus

Method of forming an interconnect structure having an enlarged region

Semiconductor device

Semiconductor device having a multilayer interconnection structure

Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation

Self-aligned nano-structures

Method of forming metal interconnections of semiconductor device

Semiconductor device and a method of manufacturing the same

Stacked via structure for metal fuse applications

Semiconductor device

Semiconductor device and a method of manufacturing the same

Semiconductor device and method of manufacturing the same

Semiconductor device and a method of manufacturing the same

Semiconductor device and fabrication method therefor

Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

Methods of patterning materials

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Electrochemical plating

SEMICONDUCTOR DEVICE WITH RESISTANCE CIRCUIT

Redundancy design with electro-migration immunity and method of manufacture

Two-track cross-connect in double-patterned structure using rectangular via

Semiconductor device with interconnection connecting to a via

Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

Method for manufacturing semiconductor device

Vias between conductive layers to improve reliability

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified RF power ramp-up

Semiconductor apparatus having power through holes connected to power pattern

Anchored conductive via and method for forming

Semiconductor structures having improved contact resistance

Method to fabricate copper wiring structures and structures formed thereby

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of manufacturing a semiconductor device

SEMICONDUCTOR DEVICE

Semiconductor device manufacturing method and semiconductor device

Semiconductor device

WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE WIRING STRUCTURE

Semiconductor device

3D integration method using SOI substrates and structures produced thereby

High performance on-chip vertical coaxial cable, method of manufacture and design structure

Reduced number of masks for IC device with stacked contact levels

Method for making multilayer connection structure

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Semiconductor device including capacitor

Interconnect structure and method of making same

Creation of vias and trenches with different depths

Semiconductor packages and methods of fabricating the same

Storage element, storage device, and signal processing circuit

Semiconductor device with a line and method of fabrication thereof

IC having viabar interconnection and related method

Semiconductor device and method of manufacturing the same

Redundancy design with electro-migration immunity and method of manufacture

Creation of vias and trenches with different depths

Interconnection structure for an integrated circuit

Multilayer wiring substrate and method of manufacturing the same

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Integrated circuit package connected to a data transmission medium

Anchored damascene structures

Stacked package structure including insulating layer between two stacked packages

Method for metal correlated via split for double patterning

Metal containing sacrifice material and method of damascene wiring formation

Semiconductor structures having improved contact resistance

Thin film resistors and methods of manufacture

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRIC DEVICE

Electromigration resistant via-to-line interconnect

Semiconductor device and method of manufacturing the same

Integrated circuit with protection from copper extrusion

Accessing or interconnecting integrated circuits

Interconnects for stacked non-volatile memory device and method

Apparatus, system, and method for wireless connection in integrated circuit packages

Through level vias and methods of formation thereof

Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall

Microelectronic device provided with an array of elements made from a conductive polymer with a positive temperature coefficient

Interconnect structure for high frequency signal transmissions

Slot-shielded coplanar strip-line compatible with CMOS processes

Structure of power grid for semiconductor devices and method of making the same

Power/ground layout for chips

Semiconductor device and method of manufacturing the same

Pad structure having contact bars extending into substrate and wafer having the pad structure

Adhesive bonding composition and method of use

Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film

Metal wiring structures for uniform current density in C4 balls

Electronic component having encapsulated wiring board and method for manufacturing the same

Methods and architectures for bottomless interconnect vias

Electrical fuse structure and method of fabricating same

Semiconductor device for effectively disperse heat generated from heat generating device

Bumpless build-up layer package with pre-stacked microelectronic devices

Carbon nanotube interconnection and manufacturing method thereof

Methods of forming openings

Power and ground routing of integrated circuit devices with improved IR drop and chip performance

Semiconductor device and manufacturing method thereof

Nonvolatile semiconductor memory device including pillars buried inside through holes

Impedance controlled electrical interconnection employing meta-materials

Seal ring structure with metal pad

Monolithic microwave integrated circuit

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Devices formed with dual damascene process

Method of forming a memory device

Non-lithographic formation of three-dimensional conductive elements

Method of chip package build-up

Semiconductor device and manufacturing method thereof

Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same

Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die

System comprising a semiconductor device and structure

Semiconductor device structures including damascene trenches with conductive structures and related method

Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction

METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE

Wiring board, semiconductor device, and manufacturing methods thereof

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY

Semiconductor device having a multilayer structure

Conductive via structures for routing porosity and low via resistance, and processes of making

Metal thin film connection structure, manufacturing method thereof and array substrate

Semiconductor integrated circuit with multi-cut via and automated layout method for the same

Semiconductor apparatus

ULTRA-LOW POWER SWNT INTERCONNECTS FOR SUB-THRESHOLD CIRCUITS

Microelectronic packages having cavities for receiving microelectronic elements

Semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE

Interconnect structure to reduce stress induced voiding effect

Fluorine depleted adhesion layer for metal interconnect structure

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation

Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die

SEMICONDUCTOR DEVICE

Semiconductor device for preventing crack in pad region and fabricating method thereof

Semiconductor device comprising variable-sized contact, method of forming same, and apparatus comprising same

SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD