CMOS device with double-sided terminals and method of making the same

Through silicon vias for semiconductor devices and manufacturing method thereof

Packaging substrate and method for manufacturing same

Copper based nitride liner passivation layers for conductive copper structures

Integrated circuit package with printed circuit layer

Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells

Semiconductor devices having compact footprints

Circuit structures and methods of fabrication with enhanced contact via electrical connection

Wide pin for improved circuit routing

Manganese oxide hard mask for etching dielectric materials

Semiconductor devices with multilayer flex interconnect structures

SEMICONDUCTOR DEVICE HAVING INSULATING LAYERS CONTAINING OXYGEN AND A BARRIER LAYER CONTAINING MANGANESE

Electronic device

Package substrates with multiple dice

Semiconductor package with single sided substrate design and manufacturing methods thereof

Three dimension structure memory

Dual damascene dual alignment interconnect scheme

Three-dimensional vertically interconnected structure and fabricating method thereof

INTEGRATED CIRCUIT PACKAGE WITH AN INTERPOSER FORMED FROM A REUSABLE CARRIER SUBSTRATE

IINTEGRATED CIRCUIT PACKAGE USING SILICON-ON-OXIDE INTERPOSER SUBSTRATE WITH THROUGH-SILICON VIAS

Structure and method for making crack stop for 3D integrated circuits

Semiconductor device having metal interconnections

High frequency switch module

Contact plug penetrating a metallic transistor

Low-stress vias

OPTICAL WIRING SUBSTRATE, MANUFACTURING METHOD OF OPTICAL WIRING SUBSTRATE AND OPTICAL MODULE

Semiconductor device

Semiconductor package having embedded semiconductor elements

Multichip integration with through silicon via (TSV) die embedded in package

Providing a void-free filled interconnect structure in a layer of package substrate

Composite reconstituted wafer structures

Interconnect structures containing nitrided metallic residues

Interconnect with hybrid metallization

Interconnect structures containing nitrided metallic residues

Composite reconstituted wafer structures

Composite reconstituted wafer structures

Vertical electronic fuse

Through substrate via structures and methods of forming the same

Semiconductor device having groove-shaped via-hole

CONTACT LINER AND METHODS OF FABRICATION THEREOF

Interconnect structure and method of making same

Conductive via structures for routing porosity and low via resistance, and processes of making

Systems and methods for stacked semiconductor memory devices

Reliable packaging and interconnect structures

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE

Electrical fuse structure and method of formation

Semiconductor interconnect structures

Semiconductor device having a multilayer interconnection structure

Semiconductor device and manufacturing method thereof

Through-vias for wiring layers of semicondutor devices

Semiconductor device and fabrication method

Semiconductor device with air gap and method of fabricating the same

Semiconductor device having groove-shaped via-hole

SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME

Wiring substrate and semiconductor device

Chip-on-film package and device assembly including the same

Semiconductor apparatus

Conductive structures, systems and devices including conductive structures and related methods

Multilevel interconnect structures and methods of fabricating same

Semiconductor packages and methods of fabricating the same

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Semiconductor packages including a heat spreader and methods of forming the same

Semiconductor device having groove-shaped via-hole

Semiconductor devices and methods of manufacturing the same

Through-wafer via device and method of manufacturing the same

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Semiconductor device having groove-shaped via-hole

Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto

Stacked structure having a protective layer between an insulation layer and wiring

Semiconductor device and semiconductor system including the same

Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system

Semiconductor device, method for manufacturing same, and electronic component

Forming array contacts in semiconductor memories

Semiconductor device

THROUGH-SUBSTRATE VIA WITH A FUSE STRUCTURE

Interlayer conductor structure and method

Wafer level chip scale packaging intermediate structure apparatus and method

Stress tuning for reducing wafer warpage

Interconnect structure for stacked device

Method and apparatus for back end of line semiconductor device processing

Interconnect structure with kinked profile

Semiconductor structure

Dual damascene gap filling process

Stubby pads for channel cross-talk reduction

Patterning approach for improved via landing profile

Interconnect structure and method of forming same

Semiconductor device and manufacturing method having copper interconnects with metal film, barrier metal, and metal caps

Semiconductor Device

Conductive line system and process

System and method for optimization of an imaged pattern of a semiconductor device

Semiconductor device

Nonvolatile semiconductor memory device and method of manufacturing the same

Interconnect structure for connecting dies and methods of forming the same

Layout for reticle and wafer scanning electron microscope registration or overlay measurements

Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

Semiconductor integrated circuit

Mitigating electromigration effects using parallel pillars

Method of fabricating an air gap using a damascene process and structure of same

Semiconductor component comprising copper metallizations

Method of preventing a pattern collapse

Semiconductor device using carbon nanotube, and manufacturing method thereof

Method of forming stacked trench contacts and structures formed thereby

Stacked packages having through hole vias

Semiconductor device and method for manufacturing the semiconductor device

Thermally-optimized metal fill for stacked chip systems

Power MOS transistor with improved metal contact

Bumpless build-up layer package with pre-stacked microelectronic devices

Integrated circuit interconnects and methods of making same

Semiconductor device and method of forming micro-vias partially through insulating material around bump interconnect

Semiconductor devices including WiSX

Integrated circuits and methods of forming the same with multi-level electrical connection

Device bond pads over process control monitor structures in a semiconductor die

Tapered sidewall conductive lines and formation thereof

Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation

Elongated via structures

Interconnection structure for an integrated circuit

Stacked multilayer structure and manufacturing method thereof

THREE-DIMENSIONAL MONOLITHIC ELECTRONIC-PHOTONIC INTEGRATED CIRCUIT

Semiconductor device and method of fabricating the same

INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME

Semiconductor devices having through silicon vias and methods of fabricating the same

Non-lithographic formation of three-dimensional conductive elements

MRAM with sidewall protection and method of fabrication

Techniques for enhancing fracture resistance of interconnects

Integrated circuit package with active interposer

Mitigating pattern collapse

Through silicon vias for semiconductor devices and manufacturing method thereof

Chip with through silicon via electrode and method of forming the same

PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE

Method of manufacturing semiconductor device

Semiconductor device

Forming vias and trenches for self-aligned contacts in a semiconductor structure

Semiconductor devices and methods of manufacture thereof

Three dimensional stacked structure for chips

Method of manufacturing interconnection and semiconductor device

Semiconductor device including passivation layer encapsulant

Ultrathin buried die module and method of manufacturing thereof

Cobalt based interconnects and methods of fabrication thereof

Package on package (PoP) bonding structures

Capacitor in Post-Passivation structures and methods of forming the same

Modified via bottom for BEOL via efuse

Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith

Surface modified TSV structure and methods thereof

Semiconductor devices comprising interconnect structures and methods of fabrication

Barrier for through-silicon via

Semiconductor device including contact plug and method of manufacturing the same

Semiconductor device

Interconnect structure and fabrication method

INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF

Method for fabricating interconnect structure

Semiconductor device

Protecting layer in a semiconductor structure

Semiconductor device with a multilayer wire

Semiconductor constructions and methods of forming interconnects

Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone

Semiconductor interconnect structures

Crosstalk polarity reversal and cancellation through substrate material tuning

Data transfer across power domains

Clock distribution network for 3D integrated circuit

Semiconductor devices having guard ring structure and methods of manufacture thereof

Semiconductor device including two groove-shaped patterns that include two bent portions

Semiconductor device including two groove-shaped patterns

Strained transistor structure

Through-substrate via formation with improved topography control

Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor

Semiconductor memory device including a slit

Low resistance stacked annular contact

Semiconductor structure and manufacturing method of the same

Interconnect with titanium—oxide diffusion barrier

Integrated circuit chips having vertically extended through-substrate vias therein

Nitride semiconductor device

BEOL structures incorporating active devices and mechanical strength

Photoactive compound gradient photoresist

Semiconductor device having a high frequency external connection electrode positioned within a via hole

Semiconductor structures and methods of manufacturing the same

Self-enclosed asymmetric interconnect structures

Packaging substrate, method for manufacturing same, and chip packaging body having same

Semiconductor device and method of manufacturing the same

Beol structures incorporating active devices and mechanical strength

Bond pad structure and method of manufacturing the same

System of chip package build-up

TSV formation

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Embedded chip packages and methods for manufacturing an embedded chip package

CD control

Dual hard mask lithography process

Semiconductor structure and method of generating masks for making integrated circuit

Cooling channels in 3DIC stacks

Enhanced electrochemical deposition filling

Three dimensional stacked semiconductor structure and method for manufacturing the same

Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability

Semiconductor device

Semiconductor device having a self-forming barrier layer at via bottom

Circuit boards, methods of fabricating the same, and semiconductor packages including the circuit boards

Contact and via interconnects using metal around dielectric pillars

Directed self assembly of block copolymers to form vias aligned with interconnects

Localized high density substrate routing

Chip-size, double side connection package and method for manufacturing the same

Electrical fuse and method of fabricating the same

Reliable interconnect for semiconductor device

Encapsulated damascene interconnect structure for integrated circuits

Mold chase for integrated circuit package assembly and associated techniques and configurations

Method for forming a vertical electrical connection in a layered semiconductor structure

Interconnect structures comprising flexible buffer layers

Encapsulated metal interconnect

PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME

Apparatus and method for high density multi-chip structures

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Post passivation interconnect structures and methods for forming the same

Semiconductor device with protective layer over exposed surfaces of semiconductor die

Electronic fuse vias in interconnect structures

Gate contact structure over active gate and method to fabricate same

Apparatuses including scalable drivers and methods

Semiconductor interconnect structure having enhanced performance and reliability

Semiconductor device having barrier metal layer

E-fuse structures and methods of manufacture

Semiconductor package including a substrate and an interposer

Overlay-tolerant via mask and reactive ion etch (RIE) technique

Semiconductor device and manufacturing method thereof

Interconnect structure and method

Semiconductor device and fabricating method thereof

Semiconductor device with low resistance wiring and manufacturing method for the device

Patterned graphene structures on silicon carbide

Semiconductor package with interposer

Multi-level vertical plug formation with stop layers of increasing thicknesses

Self-aligned interconnection for integrated circuits

Forming array contacts in semiconductor memories

Semiconductor device and method for fabricating the same

Method to improve fine Cu line reliability in an integrated circuit device

Substrate structure and method for manufacturing same

Semiconductor structure and method for fabricating semiconductor layout

Apparatus, system, and method for wireless connection in integrated circuit packages

ELECTRONIC STRUCTURE CONTAINING A VIA ARRAY AS A PHYSICAL UNCLONABLE FUNCTION

Stacked multilayer structure and manufacturing method thereof

Semiconductor devices comprising GSG interconnect structures

Method for forming an electrical connection between metal layers

Method for forming an electrical connection between metal layers

Semiconductor device and method of fabricating the same

Two-track cross-connect in double-patterned structure using rectangular via

Semiconductor device and method for fabricating the same

Semiconductor devices having through electrodes and methods of fabricating the same

Method of fabricating a profile control in interconnect structures

Method and structure of forming backside through silicon via connections

SRAM cell connection structure

Trap rich layer with through-silicon-vias in semiconductor devices

Bonding method using porosified surfaces for making stacked structures

Metallization of fluorocarbon-based dielectric for interconnects

Integrated circuit interconnects and methods of making same

Semiconductor device with embedded interconnect pad

Copper contact plugs with barrier layers

Ternary tungsten boride nitride films and methods for forming same

Low cost anti-fuse structure and method to make same

Semiconductor package with single sided substrate design and manufacturing methods thereof

Integrated circuit device having through-silicon-via structure

Vertical type semiconductor device and method for manufacturing the same

Method for forming interlayer connectors in a three-dimensional stacked IC device

Semiconductor substrate and method of fabricating the same

Hybrid interconnect scheme including aluminum metal line in low-k dielectric

Semiconductor device and fabricating process for the same

Low cost anti-fuse structure

Method of forming vertical electronic fuse interconnect structures including a conductive cap

Multi-chip package and method of manufacturing the same

Methods and structures for multiport memory devices

Package substrates with multiple dice

Hybrid package transmission line circuits

Voids in interconnect structures and methods for forming the same

Semiconductor devices and methods of manufacturing the same

Semiconductor device with output circuit and pad

Apparatus, system, and method for wireless connection in integrated circuit packages

Semiconductor device

Semiconductor memory device, memory system including the same and method of manufacturing the same

Calibration kits for RF passive devices

Dual damascene dual alignment interconnect scheme

Through-silicon via and fabrication method thereof

Semiconductor devices, methods of manufacture thereof, and methods of forming resistors

Via density and placement in radio frequency shielding applications

Three dimensional memory structure

Integrated circuit including wire structure, related method and design structure

Re-distribution Layer Via Structure and Method of Making Same

Semiconductor processing method and semiconductor structure

Capacitor for interposers and methods of manufacture thereof

SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE

Substrate-less stackable package with wire-bond interconnect

INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER

METHODS OF FORMING CONDUCTIVE CONTACTS FOR A SEMICONDUCTOR DEVICE

Semiconductor packages including molding layers

Semiconductor interconnect structure

Semiconductor package including an antenna formed in a groove within a sealing element

Semiconductor device

Semiconductor device having mesh-pattern wirings

Elongated via structures

Fabrication of semiconductor device including chemical mechanical polishing

3D integrated circuit system with connecting via structure and method for forming the same

Semiconductor devices including conductive features with capping layers and methods of forming the same