Self-aligned patterning with colored blocking and structures resulting therefrom

Package structure and method of fabricating the same

Semiconductor device and manufacturing method thereof

Integrated circuit structures having linerless self-forming barriers

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Semiconductor structure with staggered selective growth

Semiconductor memory device

Three-dimensional memory devices having through array contacts and methods for forming the same

Semiconductor device and method for fabricating the same

Backside contact for thermal displacement in a multi-wafer stacked integrated circuit

Interconnect structure

Package structure having conductive patterns with crystal grains copper columnar shape and method manufacturing the same

Semiconductor device including back side power supply circuit

Interconnect structure and method for forming the same

Manufacturing method of memory device

SEMICONDUCTOR MEMORY DEVICE

Placing top vias at line ends by selective growth of via mask from line cut dielectric

Assemblies comprising memory cells and select gates

Via contact patterning method to increase edge placement error margin

Interconnect structure and method for forming the same

Selective recessing to form a fully aligned via

Method of manufacturing a semiconductor device having a source/drain contact plug with a recessed portion using a mask pattern layer

Method and IC design with non-linear power rails

Skip-via proximity interconnect

Trapezoidal interconnect at tight BEOL pitch

Memory device

Semiconductor device and method for fabricating the same

Integrated assemblies comprising memory cells and shielding material between the memory cells

Semiconductor device packages and methods of manufacturing the same

Semiconductor device

Patterning approach for improved via landing profile

Self aligned gratings for tight pitch interconnects and methods of fabrication

Interconnect clip with angled contact surface and raised bridge

Interconnect structure and method

Bonding alignment marks at bonding interface

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Scaled gate contact and source/drain cap

Vertical non-volatile memory devices and methods of programming the same

Three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same

3D NAND memory device and method of forming the same

Semiconductor and manufacturing method of the same

Semiconductor device

Semiconductor device with exposed input/output pad in recess

Electronic device having a curved portion between a plurality of conductive portions on a substrate

Frame-array interconnects for integrated-circuit packages

Structure and formation method of chip package with fan-out feature

Semiconductor device and method of manufacture

Vertical memory devices

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Transistors including two-dimensional materials

Semiconductor device package and method of manufacturing the same

BARRIER MATERIALS BETWEEN BUMPS AND PADS

Methods for reducing dual damascene distortion

Semiconductor device and oscillator

Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same

Interconnect structures with low-aspect-ratio contact vias

Semiconductor structure and manufacturing method thereof

Semiconductor package and semiconductor device

Semiconductor chip including low-k dielectric layer

Semiconductor structure and manufacturing method thereof

Barrier-Less Structures

3D semiconductor device and structure

Microelectronic devices including an oxide material between adjacent decks, electronic systems, and related methods

Semiconductor device with air gap structure and method for preparing the same

Apparatus comprising aluminum interconnections, memory devices comprising interconnections, and related methods

Prevention of contact bottom void in semiconductor fabrication

FinFET device with contact over dielectric gate

Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric

Semiconductor memory device

Die stacks and methods forming same

Vertical semiconductor devices

Method of testing wafer

Helmet structures for semiconductor interconnects

Semiconductor device, package structure including a heat dissipation element having a conductive base and a plurality of antenna patterns and method of fabricating the semiconductor device

Semiconductor device

Dual metal silicide structures for advanced integrated circuit structure fabrication

Top via interconnects with wrap around liner

MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION

Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same

Electronic apparatus and manufacturing method thereof

Semiconductor device package and method for manufacturing the same

Integrated circuit device with through interconnect via and methods of manufacturing the same

Adjustable via dimension and chamfer angle

Interconnect structure having an etch stop layer over conductive lines

Semiconductor structure and method for manufacturing the same

Memory cell with top electrode via

Vertical semiconductor device with steep subthreshold slope

Integrated circuit having a high cell density

Interconnect and memory structures formed in the BEOL

Semiconductor device and method of manufacturing the same

Semiconductor memory device and manufacturing method of the semiconductor memory device

Semiconductor device and method for fabricating the same

Self-aligned spacers and method forming same

Three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device

Semiconductor devices

Package structure, chip structure and method of fabricating the same

Semiconductor structure and fabrication method thereof

Semiconductor device and method of manufacturing the same

Methods and apparatus for forming dual metal interconnects

Dual-gate trench IGBT with buried floating P-type shield

Self-aligned contacts in three-dimensional memory devices and methods for forming the same

Semiconductor devices including contact plugs

Integrated circuit having a single damascene wiring network

Plugs for interconnect lines for advanced integrated circuit structure fabrication

Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof

Standard cell and an integrated circuit including the same

Interconnect structures having lines and vias comprising different conductive materials

Method for manufacturing an interconnect structure having a selectively formed bottom via

Memory cell structure of a three-dimensional memory device

Semiconductor devices and methods of manufacturing semiconductor devices

Semiconductor structure and manufacturing method thereof

Semiconductor device

Integrated circuit device and method of manufacturing the same

Semiconductor packages including through holes and methods of fabricating the same

Interconnect structure and manufacturing method for the same

Integrated circuit device

Staircase formation in three-dimensional memory device

Semiconductor device

Variable pitch and stack height for high performance interconnects

Sidewall interconnect metallization structures for integrated circuit devices

Back end of line via to metal line margin improvement

Semiconductor die with conversion coating

SUBSTRATE FOR AN ELECTRONIC DEVICE

Semiconductor device and a method of manufacturing the same

Interconnect structure and method of forming the same

Semiconductor structure

Photonic integrated package and method forming same

Memory cell with top electrode via

Memory device and manufacturing method thereof

Three-dimensional flash memory device including channel structures having enlarged portions

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

Self-aligned cut process for self-aligned via process window

Method for forming lead wires in hybrid-bonded semiconductor devices

High current integrated circuit-based transformer

Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure

Three-dimensional memory device with support structures in slit structures and method for forming the same

Bonded die assembly containing a manganese-containing oxide bonding layer and methods for making the same

Semiconductor device and manufacturing method thereof

Semiconductor device, associated method and layout

Semiconductor device and fabrication method for the same

Integrated circuit device with bonding structure and method of forming the same

Replacement gate structures for advanced integrated circuit structure fabrication

Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

Three-dimensional semiconductor memory devices

MULTI-DIE INTERCONNECT

Semiconductor device package with stress buffering layer and method for manufacturing the same

Semiconductor devices comprising planar waveguide transmission lines

Chemical direct pattern plating method

Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation

Metal via structure

Method of forming semiconductor structure having layer with re-entrant profile

Selective ILD deposition for fully aligned via with airgap

Vias with multiconnection via structures

Shield structure for backside through substrate vias (TSVs)

Air channel formation in packaging process

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Semiconductor package

Method and structure of metal cut

Switch branch structure

Power distribution network using buried power rail

Applications of buried power rails

Method of forming interconnection structure

Semiconductor devices having 3-dimensional inductive structures

Integrated circuit structures with contoured interconnects

Semiconductor device and method of manufacturing a semiconductor device

Method to repair edge placement errors in a semiconductor device

Interconnects with tight pitch and reduced resistance

Interconnect structure

Three-dimensional semiconductor memory device

Semiconductor structure and manufacturing method thereof

Etch barrier for microelectronic packaging conductive structures

Density-graded adhesion layer for conductors

Three-dimensional semiconductor memory device

Three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same

Semiconductor device

Package-on-package and package connection system comprising the same

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Wafer level fan-out application specific integrated circuit bridge memory stack

Anti-fuse structure and method for fabricating same, as well as semiconductor device

Interconnect structure

Semiconductor structure and forming method thereof

Semiconductor device package and method of manufacturing the same

Semiconductor device and methods of manufacturing

Multiple patterning with self-alignment provided by spacers

Semiconductor device and method for manufacturing the same, and electronic apparatus

FinFETs and methods of forming FinFETs

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Display device having notched connection wiring

Via-to-metal tip connections in multi-layer chips

Semiconductor memory device having contact element of rectangular shape

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Package structure and method of manufacturing the same

Method for forming semiconductor device with self-aligned conductive features

Semiconductor packages and methods of manufacturing the same

Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby

Semiconductor structure and method for forming a semiconductor structure

Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication

Integrated circuit device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Semiconductor device with integrated capacitor and manufacturing method thereof

LOW ASPECT RATIO INTERCONNECT

Semiconductor chip with stacked conductor lines and air gaps

Via contact, memory device, and method of forming semiconductor structure

Dual metal gate structures for advanced integrated circuit structure fabrication

Bonded assembly containing side bonding structures and methods of manufacturing the same

Die stacks and methods forming same

Semiconductor device with shielding structure for cross-talk reduction

Semiconductor devices including redistribution layers

Bonding support structure (and related process) for wafer stacking

Integrated circuits with line breaks and line bridges within a single interconnect level

Quantum dot devices

Three-dimensional memory devices and fabrication methods thereof

Integrated circuit package with integrated voltage regulator

Interconnects separated by a dielectric region formed using removable sacrificial plugs

Chip package structure and chip package method including bare chips with capacitor polar plate

Memory device and manufacturing method thereof

Tiled lateral thyristor

Semiconductor device including contacts having different heights and different widths

Vertical memory devices

Semiconductor storage device and method for manufacturing semiconductor storage device

SEMICONDUCTOR DEVICE

Manufacturing method of semiconductor package including thermal conductive block

Semiconductor package including hybrid bonding structure and method for preparing the same

Semiconductor device

Semiconductor memory device

Semiconductor package and manufacturing method of the same

Semiconductor memory device

Sensors based on a heterojunction bipolar transistor construction

Semiconductor device

Three-dimensional device with bonded structures including a support die and methods of making the same

Three-dimensional memory array including self-aligned dielectric pillar structures and methods of making the same

Semiconductor memory device

Three-dimensional memory array including self-aligned dielectric pillar structures and methods of making the same

Hybrid bonding contact structure of three-dimensional memory device

Semiconductor storage device

SEMICONDUCTOR MEMORY DEVICE

Integrated assemblies comprising memory cells and shielding material between the memory cells, and methods of forming integrated assemblies

Semiconductor device including an upper contact in contact with a side surface of an upper gate structure

Interconnection structure, semiconductor package and method of manufacturing the same

Interconnect structure with air-gaps

Bonded assembly including a semiconductor-on-insulator die and methods for making the same

Package on package and package connection system comprising the same

Semiconductor package and manufacturing method thereof

Package structure and method of manufacturing the same

Fan-out packages with warpage resistance

Semiconductor device with step-like wiring layers and manufacturing method thereof

Package structure and method of forming the same

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

Word line decoder circuitry under a three-dimensional memory array

Semiconductor storage device and method for manufacturing semiconductor storage device

Self-aligned gate endcap (SAGE) architecture having local interconnects

Redistribution layer structures for integrated circuit package

Semiconductor device and manufacturing method thereof

Semiconductor memory device having a memory cell and semiconductor layer

Semiconductor package with inner lead pattern group and method for manufacturing the semiconductor package

Trench plug hardmask for advanced integrated circuit structure fabrication

Method of semiconductor integrated circuit fabrication

Fabricating vias with lower resistance

Dielectric surface modification in sub-40nm pitch interconnect patterning

INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME

Manufacturing method of semiconductor device including conductive structure

Method for securing an integrated circuit upon making it

3D NAND word line connection structure

Techniques for forming vias and other interconnects for integrated circuit structures

WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Chip packaging structure

Chip package and method of forming the same

Semiconductor package having a semiconductor device bonded to a circuit substrate through connection terminals and dummy conductors and method of manufacturing the same

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Vertical memory device with a channel layer in a stacked dielectric layer

Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Bonded assembly including a semiconductor-on-insulator die and methods for making the same

Semiconductor chip

SEMICONDUCTOR STORAGE DEVICE AND INSPECTION METHOD

Three dimensional memory device and method for fabricating the same

Integrated circuit

Layout method

Vertical memory devices

SEMICONDUCTOR MEMORY DEVICE

Three-dimensional memory device containing channels with laterally pegged dielectric cores

Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same

Three-dimensional semiconductor device

Semiconductor device, package structure and method of fabricating the same

Semiconductor device with copper interconnections

Method for forming semiconductor device structure

Staircase formation in three-dimensional memory device

Semiconductor device and method for fabricating the same

Semiconductor device

Memory cell structure of a three-dimensional memory device

Semiconductor device, circuit board structure and manufacturing method thereof

Semiconductor device bonded by bonding pads

Metal patterning for internal cell routing

Vertical memory devices including stacked conductive lines and methods of manufacturing the same

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Package structure and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device including interconnections having different structures and method of fabricating the same