Semiconductor device and method for manufacturing same

MULTI-USE PACKAGE ARCHITECTURE

Interconnect structure having an etch stop layer over conductive lines

Layer stack of component carrier material with embedded components and common high temperature robust dielectric structure

METAL-OXIDE SEMICONDUCTOR (MOS) DEVICE WITH THICK OXIDE

Concurrent formation of memory openings and contact openings for a three-dimensional memory device

Three-dimensional memory device containing replacement contact via structures and method of making the same

Memory cell array with large gate widths

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Semiconductor device and method for manufacturing the same

Multi-tier three-dimensional memory device containing differential etch rate field oxides and method of making the same

Semiconductor structure and fabrication method thereof

Semiconductor device

Vertical gate semiconductor device with steep subthreshold slope

SUBSTRATE HAVING NON-THROUGH HOLE

Selective ILD deposition for fully aligned via with airgap

Memory devices including stair step or tiered structures and related methods

SGT-including pillar-shaped semiconductor device and method for producing the same

Semiconductor device with shielding structure for cross-talk reduction

Interconnect structure with air gaps

Semiconductor structure with ultra thick metal and manufacturing method thereof

Semiconductor device including buried insulation layer and manufacturing method thereof

Interconnect structure and method

Method of manufacturing wafer level low melting temperature interconnections

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same

Power distribution circuitry

Increased contact alignment tolerance for direct bonding

Methods for reducing dual damascene distortion

Hybrid copper structure for advance interconnect usage

Standard cell architecture for gate tie-off

Display device

Semiconductor package and method of manufacturing the same

Trench MOSFET with self-aligned body contact with spacer

Method and structure to construct cylindrical interconnects to reduce resistance

CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING AN ELECTROLYTIC NICKEL LAYER

Method for producing pillar-shaped semiconductor device

Semiconductor integrated circuitry

Semiconductor devices

Methods of filling horizontally-extending openings of integrated assemblies

SEMICONDUCTOR DEVICE

Forming dual metallization interconnect structures in single metallization level

Semiconductor device

Transistor structure in low noise amplifier

Skip via structures

Display device having notched connection wiring

Semiconductor device

Power semiconductor device and method for manufacturing same

Vertically-strained silicon device for use with a perpendicular magnetic tunnel junction (PMTJ)

Contact structures and methods of making the contact structures

Semiconductor devices including a capping layer

Dissimilar material interface having lattices

Pitch translation architecture for semiconductor package including embedded interconnect bridge

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor devices including a stair step structure, and related methods

Methods of forming staircase structures

Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration

Semiconductor device packages and stacked package assemblies including high density interconnections

Semiconductor device packages and stacked package assemblies including high density interconnections

Radio-frequency isolation cavities and cavity formation

Topside radio-frequency isolation cavity configuration

Forming dual metallization interconnect structures in single metallization level

Semiconductor devices having electrically and optically conductive vias, and associated systems and methods

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Method of fabricating a semiconductor package using an insulating polymer layer

Semiconductor devices

Inverted staircase contact for density improvement to 3D stacked devices

VERTICAL MEMORY DEVICES

SEMICONDUCTOR DEVICE AND METHOD WITH MULTIPLE REDISTRIBUTION LAYER AND FINE LINE CAPABILITY

Field effect transistor and method of making

Substrate structure and electronic device having coarse redistribution layer electrically connected to fine redistribution layer

Semiconductor devices

Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure

Interconnection structure and method for manufacturing same

Selective ILD deposition for fully aligned via with airgap

Method for fabricating a folded channel trench MOSFET

Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit

Epitaxial source or drain structures for advanced integrated circuit structure fabrication

Gate line plug structures for advanced integrated circuit structure fabrication

Replacement gate structures for advanced integrated circuit structure fabrication

Conductive pattern with tapered angle, display device including the same, and method of manufacturing conductive pattern

Dual metal gate structures for advanced integrated circuit structure fabrication

Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Via sizing for IR drop reduction

Interconnect structures and methods of forming the same

BEOL integration with advanced interconnects

Middle-end-of-line strap for standard cell

Integrated circuit package substrate

Dual metal silicide structures for advanced integrated circuit structure fabrication

Prevention of contact bottom void in semiconductor fabrication

Trench plug hardmask for advanced integrated circuit structure fabrication

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Plugs for interconnect lines for advanced integrated circuit structure fabrication

Method of forming semiconductor structure having layer with re-entrant profile

Continuous gate and fin spacer for advanced integrated circuit structure fabrication

Trench isolation for advanced integrated circuit structure fabrication

Method for forming interconnect structure

Contact over active gate structures for advanced integrated circuit structure fabrication

Semiconductor structure and method for forming the same

Semiconductor devices

Semiconductor device and manufacturing method thereof

Semiconductor device, layout design method for the same and method for fabricating the same

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Semiconductor device

Semiconductor device and forming method thereof

Interconnect structure and method of forming the same

Low aspect ratio interconnect

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Patterning approach for improved via landing profile

Semiconductor devices

Two-Dimensional Via Pillar Structures

Semiconductor device

Via structure and methods thereof

Method for forming an aligned mask

Methods of forming semiconductor device structures

Electronic device and method for fabricating the same

Biconvex low resistance metal wire

Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures

Semiconductor device and manufacturing method thereof

Heterojunction semiconductor device for reducing parasitic capacitance

Semiconductor devices including contact plugs

FinFETs and methods of forming FinFETs

Three-dimensional memory devices and fabricating methods thereof

Semiconductor structure

Metal on both sides with clock gated-power and signal routing underneath

Integrated circuits including via array and methods of manufacturing the same

Stair contact structure, manufacturing method of stair contact structure, and memory structure

Method for forming conductive lines

Conductive vias in semiconductor packages and methods of forming same

Systems and methods to enhance passivation integrity

Radio-frequency isolation using porous silicon

Integrated circuit with conductive line having line-ends

Electrically-verifiable fuses and method of fuse verification

Method for producing pillar-shaped semiconductor device

Semiconductor device with superior crack resistivity in the metallization system

INTERCONNECTION STRUCTURE LINED BY ISOLATION LAYER

Fuse structure having air dummy fuses and semiconductor device including the same

Method of manufacturing semiconductor device with multi wire structure

Techniques based on electromigration characteristics of cell interconnect

Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Semiconductor device

Semiconductor device with integrated capacitor and manufacturing method thereof

Methods of forming semiconductor devices

Array substrate and display device

Memory cell structure of a three-dimensional memory device

Semiconductor device having an inter-layer via (ILV), and method of making same

Method of fabricating integrated circuit having staggered conductive features

Interconnection structure and method for forming the same

Integrated circuit having a high cell density

Dense redistribution layers in semiconductor packages and methods of forming the same

Semiconductor structure and manufacturing method thereof

Laterally extended conductive bump buffer

Semiconductor device and method of manufacturing the semiconductor device

Fully aligned via in ground rule region

Semiconductor device and a method of manufacturing the same

High current lateral GaN transistors with scalable topology and gate drive phase equalization

Integrated device comprising a capacitor and inductor structure comprising a shared interconnect for a capacitor and an inductor

Semiconductor memory device

Three-dimensional memory devices and methods for forming the same

Three-dimensional NAND memory device with source line comprising metallic and semiconductor layers

SRAM cell with T-shaped contact

Connection structure of semiconductor device and manufacturing method thereof

Package substrate and semiconductor package including the same

Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom via

Stacked substrate structure with inter-tier interconnection

Semiconductor device

Semiconductor device and method for manufacturing the same

Structure for standard logic performance improvement having a back-side through-substrate-via

Interconnect structure for semiconductor device and methods of fabrication thereof

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies

Interconnect structure for semiconductor device and methods of fabrication thereof

Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies

Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch

Structure and formation method of semiconductor device with self-aligned conductive features

Integrated passive device and fabrication method using a last through-substrate via

Method and IC design with non-linear power rails

Three-dimensional memory device with straddling drain select electrode lines and method of making thereof

Fence structure to prevent stiction in a MEMS motion sensor

Hybrid bonding contact structure of three-dimensional memory device

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Chip structure including heating element

Word line decoder circuitry under a three-dimensional memory array

Semiconductor device and method of producing semiconductor device

Semiconductor device including dummy contact

METHOD OF INCREASING EMBEDDED 3D METAL-INSULATOR-METAL (MIM) CAPACITOR CAPACITANCE DENSITY FOR WAFER LEVEL PACKAGING

Semiconductor devices

Semiconductor device

Semiconductor structure and method for fabricating the same

Semiconductor device and a corresponding method of manufacturing semiconductor devices

Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation

Semiconductor device including dielectric layer

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Semiconductor package and method of manufacturing the same

Semiconductor device

Chip package interaction (CPI) back-end-of-line (BEOL) monitoring structure and method

Interconnect structure

Semiconductor device resistor including vias and multiple metal layers

Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on First-Metal Vertical Grid

Semiconductor device including a buffer layer structure for reducing stress

Method for forming semiconductor device structure with graphene layer

Semiconductor device

Semiconductor device and manufacturing method thereof

Three-dimensional semiconductor device and method of fabricating the same

Heterojunction semiconductor device for reducing parasitic capacitance

Power gating for three dimensional integrated circuits (3DIC)

Semiconductor device with shielding structure for cross-talk reduction

Integrated circuit structure having gate contact and method of forming same

Structure and method for improving high voltage breakdown reliability of a microelectronic device

Self-aligned spacers and method forming same

Metallization lines on integrated circuit products

Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid

Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid

Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on First-Metal Vertical Grid

SEMICONDUCTOR APPARATUS

VERTICAL MEMORY DEVICE

Semiconductor device having shared power line connections and method of manufacturing the same

Via rail solution for high power electromigration

Methods of manufacturing a semiconductor device

Step height reduction of memory element

Wrapped contacts with enhanced area

Method of manufacturing a semiconductor device including an LDMOS transistor

Metal gate and contact plug design and method forming same

Capacitor having multiple graphene structures

Static random access memory (SRAM) device

Semiconductor device having contact plug and method of forming the same

Conductive vias in semiconductor packages and methods of forming same

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

Semiconductor device and manufacturing method thereof

Method of integrated circuit fabrication with dual metal power rail

Chemical clean of semiconductor device

Metal-oxide semiconductor (MOS) device with thick oxide

Dynamic random access memory and method of manufacturing the same

Vertical gate semiconductor device with steep subthreshold slope

Integrated circuit packages with conductive element having cavities housing electrically connected embedded components

Interconnection structure and method for forming the same

Advanced copper interconnects with hybrid microstructure

Mitigating pattern collapse

Composite dielectric interface layers for interconnect structures

Dielectric film for semiconductor fabrication

IC structure with interface liner and methods of forming same

Semiconductor device structure with resistive element

Semiconductor device with coils in different wiring layers

MULTI-LAYER BARRIER FOR CMOS UNDER ARRAY TYPE MEMORY DEVICE AND METHOD OF MAKING THEREOF

Three dimensional storage cell array with highly dense and scalable word line design approach

Method for contacting a metallic contact pad in a printed circuit board and printed circuit board

Techniques for creating a local interconnect using a SOI wafer

Vertical fin with a gate structure having a modified gate geometry

Semiconductor device and method of manufacturing the same

Vertical fin with a gate structure having a modified gate geometry

SEMICONDUCTOR DEVICES

Crack stop with overlapping vias

Semiconductor device

Surface nitridation in metal interconnects

Selective recessing to form a fully aligned via

Selective recessing to form a fully aligned via

Semiconductor device

Memory system and memory cell having dense layouts

FinFET LDMOS devices with additional dynamic control

Semiconductor structure

Semiconductor device and manufacturing method thereof

Metal patterning for internal cell routing

Semiconductor device with inductive coupling and method of manufacturing the same

Structure and formation method of interconnection structure of semiconductor device

MIDDLE-OF-LINE LOCAL INTERCONNECT STRUCTURES WITH HYBRID FEATURES

Multi-metal fill with self-align patterning

3D stacking semiconductor device

Method of manufacturing semiconductor device, and semiconductor device

BIOLOGICAL SENSING SYSTEM HAVING MICRO-ELECTRODE ARRAY

Semiconductor device and method of forming the same

Backside substrate openings in transistor devices

Copper etching integration scheme

Stacked multilayer structure and manufacturing method thereof

Semiconductor device with multi-layer metallization

Pre-spacer self-aligned cut formation

Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures

Three-dimensional memory device having conductive support structures and method of making thereof

Method of manufacturing a semiconductor device using reference pattern

LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES

Memory device and method for fabricating the same

Semiconductor device having insulating layer higher than a top surface of the substrate, and method for reducing the difficulty of filling an insulating layer in a recess

Semiconductor device

FinFET device

Semiconductor device and ball bonder

Interconnecting dies by stitch routing

Standard cell and an integrated circuit including the same

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Edge structure for multiple layers of devices, and method for fabricating the same

Method for manufacturing a semiconductor device

Semiconductor structure and fabrication method thereof

LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES

CMOS compatible fuse or resistor using self-aligned contacts

Semiconductor device and method

Semiconductor device having contacts with varying widths

Structure and method for improving high voltage breakdown reliability of a microelectronic device

Method for producing semiconductor device and semiconductor device

Asymmetric stair structure and method for fabricating the same