FinFETs and methods of forming FinFETs

Transistor structure and manufacturing method of the same

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Semiconductor device and method for manufacturing the same

Reducing metallic interconnect resistivity through application of mechanical strain

Multiple plate line architecture for multideck memory array

Wrapped source/drain contacts with enhanced area

Wrapped source/drain contacts with enhanced area

Semiconductor device including an LDMOS transistor and a resurf structure

Thin Polysilicon For Lower Off-Capacitance Of A Radio Frequency (RF) Silicon-On-Insulator (SOI) Switch Field Effect Transistor (FET)

Intra-metal capacitor and method of forming the same

Power rail for standard cell block

Semiconductor device, layout pattern and method for manufacturing an integrated circuit

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Integrated circuit device and method of manufacturing the same

Contacts having a geometry to reduce resistance

Logic cell structure with interconnection design and configuration

Structure and formation method of interconnection structure of semiconductor device structure

Non-mandrel cut formation

Body contact layouts for semiconductor structures

Display device having notched connection wiring

Three-dimensional (3D) semiconductor memory devices

Semiconductor device and method of manufacturing the same

Semiconductor device including first and second wirings

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor package assembly

Methods of manufacturing semiconductor devices

Semiconductor device having groove-shaped via-hole

Semiconductor device

Semiconductor device

Thin film element and method for manufacturing the same

Semiconductor device and manufacturing method thereof

Contacts for highly scaled transistors

Integrated circuit device

Semiconductor devices including a capping layer

Electronic device and method for fabricating the same

Group III-V device structure

Semiconductor device including resistor structure

Self-aligned via forming to conductive line and related wiring structure

Multi-level metallization interconnect structure

Methods of forming conductive structures including stair step or tiered structures having conductive portions

Increased contact alignment tolerance for direct bonding

Embedded metal-insulator-metal (MIM) decoupling capacitor in monolitic three-dimensional (3D) integrated circuit (IC) structure

Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area

Semiconductor devices and methods of fabricating the same

Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and method of making thereof

Semiconductor device for avoiding short circuit between adjacent storage nodes and manufacturing method thereof

Fan-out semiconductor package

Interconnect structure and fabricating method thereof

Semiconductor device and a method for fabricating the same

Contact hole structure and fabricating method of contact hole and fuse hole

Semiconductor device structures including stair step structures, and related semiconductor devices

Semiconductor memory device and a manufacturing method thereof

Semiconductor devices and contact plugs

Controlled resistance integrated snubber for power switching device

SEMICONDUCTOR MEMORY DEVICE INCLUDING A DUMMY WORD LINE

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Integrated circuit structure including power rail and tapping wire with method of forming same

Method for manufacturing a semiconductor device including a vertical channel between stacked electrode layers and an insulating layer

Conductive structures, wordlines and transistors

Semiconductor device including overlay patterns

Semiconductor device

Devices and methods of cobalt fill metallization

Interconnection structure and manufacturing method thereof

Semiconductor device and method of manufacturing the semiconductor device

Self-aligned spacers and method forming same

Semiconductor device with reduced via resistance

Interconnection lines having variable widths and partially self-aligned continuity cuts

Monolayer thin film capacitor and method for manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

INTEGRATED EFUSE

Method to form interconnect structure with tungsten fill

Semiconductor device and manufacturing method thereof

Airgaps to isolate metallization features

Self-aligned contact cap

Self-aligned middle of the line (MOL) contacts

Semiconductor device and manufacturing method thereof

Multi-metal fill with self-align patterning

Layout for semiconductor device including via pillar structure

Semiconductor device

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

3D NAND device with five-folded memory stack structure configuration

Integrated circuit devices

Semiconductor device and method of fabricating the same

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Redistribution layer structures for integrated circuit package

Integrated circuit having a high cell density

Semiconductor device with a conductive liner

Semiconductor device having composite structures and fabrication method thereof

FinFETs and methods of forming FinFETs

Folded channel trench MOSFET

Intra-metal capacitor and method of forming the same

Post passivation interconnect and fabrication method therefor

Integrated circuit (IC) devices with varying diameter via layer

Interconnection structures and fabrication methods thereof

Power grid structures and method of forming the same

Semiconductor package with dummy bumps connected to non-solder mask defined pads

Method of manufacturing an interconnect structure by forming metal layers in mask openings

Semiconductor device package thermal conduit

Semiconductor structure, testing and fabricating methods thereof

Method of forming interconnect structure with partial copper plating

Forming array contacts in semiconductor memories

Semiconductor memory device

Field-effect transistors with a buried body contact

Metal layer routing level for vertical FET SRAM and logic cell scaling

Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Integrated circuit chip with power delivery network on the backside of the chip

Methods of forming semiconductor device structures including staircase structures

Semiconductor device

Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit

Stress reduction apparatus with an inverted cup-shaped layer

Post spacer self-aligned cuts

Conductive layout structure including high resistive layer

Interconnect structure with air-gaps

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE

Substrate and method

Interconnect structure including air gap

Semiconductor memory device

Semiconductor memory device

Semiconductor device, manufacturing method thereof, and electronic apparatus

Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

Method for fully self-aligned via formation using a directed self assembly (DSA) process

Skip via structures

Bonding pad structure having island portions and method for manufacturing the same

MANUFACTURING METHOD OF ELECTRONIC COMPONENT

Semiconductor device having interconnection structure

Semiconductor chip and multi-chip package using thereof and method for manufacturing the same

Semiconductor devices including conductive lines and methods of forming the semiconductor devices

Semiconductor device including dielectric layer

Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a semiconductor substrate

Cavity formation in backside interface layer for radio-frequency isolation

Liner planarization-free process flow for fabricating metallic interconnect structures

IC structure including TSV having metal resistant to high temperatures and method of forming same

Display device

Semiconductor device and method of producing semiconductor device

Methods for reducing dual damascene distortion

Interlevel connectors in multilevel circuitry, and method for forming the same

Array substrate, manufacturing method thereof and display panel

Transistor with improved air spacer

Advanced metal interconnects

Dielectric film for semiconductor fabrication

Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

Methods of forming metallization lines on integrated circuit products and the resulting products

Middle end-of-line strap for standard cell

Composite dielectric interface layers for interconnect structures

Semiconductor device with air gap between wires and method for fabricating the same

Integrated circuit (IC) devices including cross gate contacts

Semiconductor device

Hybrid copper structure for advance interconnect usage

Semiconductor device and manufacturing method thereof

HETEROGENEOUS METALLIZATION USING SOLID DIFFUSION REMOVAL OF METAL INTERCONNECTS

Semiconductor memory device and method for manufacturing same

Semiconductor device and method for manufacturing same

Integrated circuit device with gate line crossing fin-type active region

Integrated circuits with high voltage devices and methods for producing the same

Trench contact resistance reduction

Formation of advanced interconnects

Contact having self-aligned air gap spacers

Trench contact resistance reduction

Surface nitridation in metal interconnects

Surface nitridation in metal interconnects

Partial metal fill for preventing extreme-low-k dielectric delamination

Radio-frequency isolation using cavity formed in interface layer

Cavity formation using sacrificial material

Conductive contacts in semiconductor on insulator substrate

Three dimensional semiconductor memory device

Semiconductor memory device and method for manufacturing the same

Semiconductor device and manufacturing method thereof

Semiconductor device including a buffer layer structure for reducing stress

Utilization of backside silicidation to form dual side contacted capacitor

Interconnect structure having subtractive etch feature and damascene feature

Semiconductor device and method for manufacturing same

Semiconductor device and method of manufacturing the same

Through via structure, semiconductor device and manufacturing method thereof

Semiconductor device

High quality deep trench oxide

Fan-out semiconductor package

Tiled-stress-alleviating pad structure

Surface treatment for semiconductor structure

Low aspect ratio interconnect

Substrate contact using dual sided silicidation

Semiconductor device with anti-fuse component including electrode over corner of insulating member

Avoiding gate metal via shorting to source or drain contacts

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Semiconductor device

Semiconductor device and method of manufacturing the same

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Vertical memory device and method of fabricating the same

Multi-level metallization interconnect structure

Integrated circuits with Peltier cooling provided by back-end wiring

Method for fabricating semiconductor device

Semiconductor devices

Power gating for three dimensional integrated circuits (3DIC)

Interconnection structure and methods of fabrication the same

Cu wiring forming method and semiconductor device manufacturing method

Semiconductor device packages and stacked package assemblies including high density interconnections

Ridged word lines for increasing control gate lengths in a three-dimensional memory device

Surface treatment for semiconductor structure

Semiconductor memory device

Semiconductor memory device

Semiconductor device and method

Dense redistribution layers in semiconductor packages and methods of forming the same

Selective recessing to form a fully aligned via

Metal gate and contact plug design and method forming same

Fan-out semiconductor package

Semiconductor device structure

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

IC structure with interface liner and methods of forming same

Semiconductor device and manufacturing method thereof

Semiconductor devices including electrically isolated patterns and method of fabricating the same

Method and structure of forming low resistance interconnects

Heterojunction semiconductor device having source and drain pads with improved current crowding

Dies-on-package devices and methods therefor

Package on-package devices with upper RDL of WLPS and methods therefor

Semiconductor device and a method of manufacturing the same

Semiconductor device having structure for improving voltage drop and device including the same

Self-aligned contact cap

Self-aligned contact cap

Interconnect structure and fabrication thereof

Memory device

Semiconductor device includes a substrate having conductive contact structures thereon

Electric fuse structure and method for fabricating the same

Vertical memory devices

Three-dimensional stacking structure

Semiconductor structures

Hybrid interconnects and method of forming the same

Semiconductor device and method of manufacturing the same

Integrated circuit structure having gate contact and method of forming same

Systems and methods to enhance passivation integrity

Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via

Manufacturing method of semiconductor device including multi-layered source layer and channel extending therethrough

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer

Cavity generation for embedded interconnect bridges utilizing temporary structures

Semiconductor device

Semiconductor device structures

Semiconductor package and manufacturing method of the same

Semiconductor contact

Method of fabricating semiconductor device

Three-dimensional memory device with amorphous barrier layer and method of making thereof

Semiconductor device including a LDMOS transistor and method

Semiconductor device including a LDMOS transistor

Semiconductor device and method of manufacturing the same

Semiconductor switch device

Surface treatment for semiconductor structure

Biconvex low resistance metal wire

Semiconductor chip and multi-chip package using thereof

Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures

Interconnect structure and method

Semiconductor chip including region having rectangular-shaped gate structures and first metal structures

Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures

Fan-out semiconductor package

POLYMER BONDING WITH IMPROVED STEP COVERAGE

Method of producing a semiconductor device with through-substrate via covered by a solder ball

Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures

Within-array through-memory-level via structures and method of making thereof

Tiled-stress-alleviating pad structure

Electronic component of integrated circuitry and a method of forming a conductive via to a region of semiconductor material

Method for forming FinFET device

Interconnect structures with enhanced electromigration resistance

Integrated circuit having staggered conductive features

Avoiding gate metal via shorting to source or drain contacts

Hardmask layer for 3D NAND staircase structure in semiconductor applications

Method of forming contact trench

Semiconductor module

Semiconductor structure and manufacturing method thereof

Multi-layer integrated circuits having isolation cells for layer testing and related methods

Semiconductor device and electronic equipment

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

Method for patterning interconnects

Method for forming conductive lines

CMOS compatible fuse or resistor using self-aligned contacts

Method of manufacturing semiconductor device and semiconductor device

Air gap over transistor gate and related method

Semiconductor device and method for fabricating the same

Contact for high-k metal gate device

Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology

Selective and non-selective barrier layer wet removal

Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface

Semiconductor device with inductively coupled coils

Structure and formation method of damascene structure

Integrated circuit and layout method

Three-dimensional semiconductor device and method of manufacturing the same

Semiconductor memory device and method for manufacturing same

Semiconductor device including interlayer support patterns on a substrate

Integrated circuit device and method of manufacturing the same

Fuse structure having multiple air dummy fuses

Semiconductor device and method for manufacturing same

Semiconductor device and method for manufacturing same

Selective and non-selective barrier layer wet removal

Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit

Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)

Semiconductor structure having etching stop layer and manufacturing method of the same

Semiconductor device structures including staircase structures, and related methods and electronic systems

Semiconductor device and method for forming the same

Semiconductor devices

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME