Semiconductor structure and process for forming plug including layer with pulled back sidewall part

Backside cavity formation in semiconductor devices

Semiconductor devices and methods of manufacturing the same

Air-gap scheme for BEOL process

Cavity formation in interface layer in semiconductor devices

Semiconductor structure and manufacturing method thereof

Semiconductor structures having an insulative island structure

Semiconductor device

Memory device and method for manufacturing the same

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Semiconductor devices including a contact structure and methods of manufacturing the same

Semiconductor arrangement and method of making the same

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device including line patterns

Patterning method for low-k inter-metal dielectrics and associated semiconductor device

Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

Stress reduction apparatus

Semiconductor devices

Integration of heat spreader for beol thermal management

Contact for high-k metal gate device

Semiconductor memory devices

Copper via with barrier layer and cap layer

Semiconductor devices including a capping layer

Semiconductor devices

Semiconductor device and method of manufacturing the same

Semiconductor device and a method of manufacturing the same

Stacked interconnect structure and method of making the same

Methods of forming wiring structures including a plurality of metal layers

Semiconductor constructions and methods of forming intersecting lines of material

Spasers to speed up CMOS processors

Non-volatile memory device having vertical structure and method of operating the same

SEMICONDUCTOR DEVICE HAVING BURIED WORDLINES

Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography

MIS (Metal-Insulator-Semiconductor) contact structures for semiconductor devices

Semiconductor device with air gap and method for fabricating the same

Semiconductor device structure and method for forming the same

Semiconductor device structure and method for forming the same

Semiconductor device

Structure and formation method of damascene structure

Semiconductor device allowing metal layer routing formed directly under metal pad

Twisted array design for high speed vertical channel 3D NAND memory

Semiconductor device and manufacturing method thereof

Stacked damascene structures for microelectronic devices

Semiconductor device with nano-gaps and method for manufacturing the same

Semiconductor device including conductive via with buffer layer at tapered portion of conductive via

3D memory structure and method for manufacturing the same

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SRAM memory cell and SRAM memory with conductive interconnect

Semiconductor device and method of manufacturing the same

FinFETs having step sided contact plugs and methods of manufacturing the same

Self-aligned via and air gap

Semiconductor device including stripe structures

System-on-chip devices and methods of designing a layout therefor

Copper etching integration scheme

Semiconductor device and method of manufacturing the same

Systems and methods to enhance passivation integrity

Interconnect structure having large self-aligned vias

Semiconductor Devices And Fabrication Methods With Improved Word Line Resistance and Reduced Salicide Bridge Formation

Metal oxide layered structure and methods of forming the same

Self-aligned integrated line and via structure for a three-dimensional semiconductor device

Reduced height M1 metal lines for local on-chip routing

Magnetic sidewalls for write lines in field-induced MRAM and methods of manufacturing them

Etchstop layers and capacitors

Angled ion beam processing of heterogeneous structure

Semiconductor device including a buffer layer structure for reducing stress

Folded ballistic conductor interconnect line

MICROELECTRONIC TRANSISTOR CONTACTS AND METHODS OF FABRICATING THE SAME

Semiconductor devices and methods for forming the same

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Metal wiring of semiconductor device and method for manufacturing the same

Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a semiconductor substrate

Method of manufacturing semiconductor device

Semiconductor device with reduced via resistance

CHIP PACKAGE AND FABRICATION METHOD THEREOF

Power gating for three dimensional integrated circuits (3DIC)

Semiconductor device with reduced via resistance

Flip chip scheme and method of forming flip chip scheme

Interconnect structure with misaligned metal lines coupled using different interconnect layer

Chip package having a laser stop structure

Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure

Subtractive etch interconnects

Semiconductor device with multi-layer metallization

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device with electro-static discharge protection device above semiconductor device area

Integrated device package comprising photo sensitive fill between a substrate and a die

Semiconductor device

Three-dimensional semiconductor memory device

Semiconductor apparatus

Optimized wires for resistance or electromigration

Integrated circuit and layered circuit provided therewith

SEMICONDUCTOR PACKAGE

Different scaling ratio in FEOL/ MOL/ BEOL

Integrated circuit device

Integrated circuit device

Electronic component and method for producing the same

Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same

Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby

Self-aligned via process flow

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Semiconductor devices and methods of manufacture thereof having guard ring structure

MULTI-LAYER TRANSMISSION LINE STRUCTURE FOR MISALIGNMENT RELIEF

Semiconductor device

Method for manufacturing copper layer

Electrically conductive interconnect including via having increased contact surface area

Semiconductor device and method

Oversized contacts and vias in layout defined by linearly constrained topology

SEMICONDUCTOR DEVICE

Semiconductor structures and fabrication method thereof

Power semiconductor module and method for manufacturing the same

Semiconductor structure and manufacturing method of the same

Vertical type memory device

Integrated circuit with elongated coupling

Power overlay structure having wirebonds and method of manufacturing same

Methods of forming an interconnect structure using a self-ending anodic oxidation

Semiconductor device

Electronic component

Graphene wiring and method for manufacturing the same

Wiring and method for manufacturing the same

Fine line space resolution lithography structure for integrated circuit features using double patterning technology

Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same

Semiconductor device and a method of manufacturing the same

Through-silicon via access device for integrated circuits

Semiconductor device

Metal cap apparatus and method

Method for producing a conductor line

Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same

Method of forming a pattern

Semiconductor device

Semiconductor device and method of manufacturing the same

Semiconductor device with reduced via resistance

Semiconductor device with coils in different wiring layers

Semiconductor device having an airgap defined at least partially by a protective structure

Method of semiconductor integrated circuit fabrication

Method of preventing pattern collapse

Metal line structure and method

Techniques for creating a local interconnect using a SOI wafer

Wafer-to-wafer bonding structure

Semiconductor chip, semiconductor package and fabricating method thereof

Semiconductor constructions

Interconnects with fully clad lines

Hybrid copper structure for advance interconnect usage

Method of forming semiconductor device having a conductive via structure

Transformer comprising a rounded coil

Interconnect structure and method of forming the same

Insulator void aspect ratio tuning by selective deposition

Combination interconnect structure and methods of forming same

Semiconductor Device and Method of Forming a Dampening Structure to Improve Board Level Reliability

Interconnect structure with footing region

Non-hierarchical metal layers for integrated circuits

Semiconductor device

Semiconductor devices comprising interconnect structures and methods of fabrication

Power gating for three dimensional integrated circuits (3DIC)

Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution

SEMICONDUCTOR DEVICES INCLUDING BULB-SHAPED TRENCHES

Method of forming a copper layer using physical vapor deposition

Metal pad offset for multi-layer metal layout

Systems and methods for high-speed, low-profile memory packages and pinout designs

Wafer having pad structure

Semiconductor device and method of producing semiconductor device

Systems and methods to enhance passivation integrity

Trench structure for high performance interconnection lines of different resistivity and method of making same

Patterning method for low-k inter-metal dielectrics and associated semiconductor device

BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE

Semiconductor device and a method increasing a resistance value of an electric fuse

Semiconductor device and manufacturing method thereof

Semiconductor arrangement comprising metal cap and dielectric layer defining air gap

Method of fabricating conductive line of a semiconductor device

Pattern between pattern for low profile substrate

Semiconductor device

Semiconductor device and a method of manufacturing the same and designing the same

Semiconductor device

Interconnect structure having large self-aligned vias

INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL

Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same

Reduced height M1 metal lines for local on-chip routing

Forming array contacts in semiconductor memories

Controlled metal extrusion opening in semiconductor structure and method of forming

Semiconductor device with thin redistribution layers

Semiconductor devices and methods of manufacturing the same

Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Functional block stacked 3DIC and method of making same

Grounding dummy gate in scaled layout design

Semiconductor device and a method of manufacturing the same

Semiconductor device with improved contact structure and method of forming same

Semicondutor device with copper plugs having different resistance values

System and method for 3D integrated circuit stacking

Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects

Semiconductor device including landing pad

Semiconductor device and method of manufacturing the same

Semiconductor device and method of manufacturing the same

Interconnect structures for substrate

Duplicate layering and routing

Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same

Power semiconductor device and method for fabricating the same

Metal-containing films as dielectric capping barrier for advanced interconnects

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Thickened stress relief and power distribution layer

Method for providing electrical connections to spaced conductive lines

Method of forming integrated circuit with conductive line having line-ends

INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

Interconnect structure for semiconductor devices

High speed differential wiring in glass ceramic MCMS

High speed differential wiring in glass ceramic MCMS

Electrically conductive device and manufacturing method thereof

Interconnect structure and method of forming same

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Semiconductor device

Interconnects having sealing structures to enable selective metal capping layers

Semiconductor device, manufacturing method thereof, and electronic apparatus

Interconnects with fully clad lines

Semiconductor device and manufacturing method for the same

Method of manufacturing semiconductor device and semiconductor device

Semiconductor device and method of manufacturing the same

Systems and methods to enhance passivation integrity

Crack stopping structure in wafer level packaging (WLP)

Semiconductor devices including multiple interconnection structures

Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures

Resistive random access memory

Singulated semiconductor structure

SOC design with critical technology pitch alignment

Semiconductor component and method of manufacture

Semiconductor device comprising capacitive element

Graphene-metal E-fuse

High performance refractory metal / copper interconnects to eliminate electromigration

Hybrid graphene-metal interconnect structures

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Interconnection wires of semiconductor devices

Semiconductor integrated circuit device

Forming array contacts in semiconductor memories

Semiconductor device and method of manufacturing the same

Multiple-patterned semiconductor device channels

Semiconductor device channels

Multiple-patterned semiconductor device channels

Semiconductor device channels

APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS

Interconnect structure with kinked profile

Chemical direct pattern plating interconnect metallization and metal structure produced by the same

Semiconductor device with vias on a bridge connecting two buses

Semiconductor integrated circuit

Interconnect structure and method of forming the same

Method of preventing a pattern collapse

Elongated via structures

Method for providing electrical connections to spaced conductive lines

Flattened substrate surface for substrate bonding

Mitigating pattern collapse

Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core

Copper etching integration scheme

Semiconductor device

Method of manufacturing semiconductor device

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Semiconductor device with a multilayer wire

Semiconductor devices having guard ring structure and methods of manufacture thereof

Low resistance stacked annular contact

Semiconductor device and manufacturing method thereof

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Interconnect structures for substrate

Semiconductor structures and methods of manufacturing the same

Pad structure

Integrated circuit formed using spacer-like copper deposition

Method for forming a vertical electrical connection in a layered semiconductor structure

Encapsulated metal interconnect

Method of manufacturing semiconductor device

ESD protection device with improved bipolar gain using cutout in the body well

Forming array contacts in semiconductor memories

Method to improve fine Cu line reliability in an integrated circuit device

Conductive line of semiconductor device

Semiconductor device

Metal wiring of semiconductor device and method for manufacturing the same

RF CMOS transistor design

Low cost anti-fuse structure and method to make same

Low cost anti-fuse structure

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacturing the same

Semiconductor device with electro-static discharge protection device above semiconductor device area

Dual-metal self-aligned wires and vias

Capacitor for interposers and methods of manufacture thereof

Curvilinear wiring structure to reduce areas of high field density in an integrated circuit

Method to resolve hollow metal defects in interconnects

METHODS OF FORMING CONDUCTIVE CONTACTS FOR A SEMICONDUCTOR DEVICE

Semiconductor device having a copper wire within an interlayer dielectric film

INTERCONNECTION OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor interconnect structure

Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits

Elongated via structures

Integrated circuit power grid with improved routing resources and bypass capacitance

Method for producing a conductor line

Rigid interconnect structures in package-on-package assemblies

Method for fabricating a coil by way of a rounded trench

Guard ring design structure for semiconductor devices

Interconnect structure having smaller transition layer via

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor devices having contacts with intervening spacers and method for fabricating the same

Semiconductor device including a stress buffer material formed above a low-k metallization system

Interconnect structures

Semiconductor device having non-planar interface between a plug layer and a contact layer

Dual-metal self-aligned wires and vias

Stress reduction apparatus with an inverted cup-shaped layer

Inductors and wiring structures fabricated with limited wiring material