Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate

Semiconductor device with modified pad spacing structure

Fan-out semiconductor package for packaging semiconductor chip and capacitors

Three dimensional storage cell array with highly dense and scalable word line design approach

Vertical air gap subtractive etch back end metal

Interconnect structure having an etch stop layer over conductive lines

Semiconductor memory device and method of manufacturing the same

Semiconductor devices including a capping layer

Method for maximizing air gap in back end of the line interconnect through via landing modification

Advanced E-fuse structure with controlled microstructure

Advanced e-Fuse structure with hybrid metal controlled microstructure

Interconnect structure including air gaps enclosed between conductive lines and a permeable dielectric layer

Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material

Semiconductor memory device and method of manufacturing the same

SEMICONDUCTOR MEMORY DEVICE

3D non-volatile memory array utilizing metal ion source

Semiconductor memory device

Semiconductor memory device

Semiconductor device and method for manufacturing semiconductor device

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Semiconductor device and a method of manufacturing the same

High power MMIC devices having bypassed gate transistors

MANUFACTURING METHOD OF MOLDED PRODUCT AND MOLDED PRODUCT

Saw resonator having negative profile metal structure and manufacturing method thereof

Semiconductor device and method of manufacturing same

Switching device

Switching device

Semiconductor device, semiconductor wafer, module, electronic device, and manufacturing method the same

Stacked non-volatile semiconductor memory device with buried source line and method of manufacture

Semiconductor device having vertical channel between stacked electrode layers and insulating layers

Semiconductor memory device

Stacked type semiconductor memory device and method for manufacturing same

Semiconductor memory device and method of manufacturing the same

Semiconductor memory device and method for manufacturing the same

Semiconductor device and method for manufacturing same

Contacts having a geometry to reduce resistance

Conductive structures, systems and devices including conductive structures and related methods

Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

Wafer-level chip-size package with redistribution layer

Semiconductor device

SEMICONDUCTOR MEMORY DEVICE

Semiconductor memory device and method for manufacturing same

Semiconductor device structures including staircase structures, and related methods and electronic systems

Hybrid metal interconnects with a bamboo grain microstructure

Hybrid metal interconnects with a bamboo grain microstructure

Low capacitance through substrate via structures

Semiconductor device including standard cell and electronic design automation method thereof

Interconnect structure and method

Monolayer thin film capacitor

Compensating for lithographic limitations in fabricating semiconductor interconnect structures

Low resistance contact structures for trench structures

Low resistance contact structures for trench structures

Semiconductor device having a wiring line with an end portion having rounded side surfaces and manufacturing method thereof

Word line decoder circuitry under a three-dimensional memory array

Semiconductor device comprising a temperature sensor, temperature sensor and method of manufacturing a semiconductor device comprising a temperature sensor

INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME

Semiconductor module and semiconductor driving device

Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization

Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof

Vertical non-volatile memory device and method of fabricating the same

Method of manufacturing a capacitor

Non-volatile memory device

Vertical field-effect-transistors having multiple threshold voltages

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Patterning approach for improved via landing profile

Semiconductor device structure with graphene layer

Fuse structure having multiple air dummy fuses

Columnar interconnects and method of making them

Semiconductor device and electronic apparatus

Magnetic sidewalls for write lines in field-induced MRAM and methods of manufacturing them

Semiconductor device, semiconductor wafer, module, electronic device, and manufacturing method thereof

Semiconductor device and method of fabricating the same

Method of manufacturing semiconductor devices and corresponding device

Semiconductor device and manufacturing method thereof

Semiconductor device and method of producing semiconductor device

Interconnect structure having substractive etch feature and damascene feature

Interconnection structure and method of forming the same

Semiconductor device structure and method for forming the same

Semiconductor having protective lines

Semiconductor device

Three-dimensional (3D) semiconductor memory devices

Method of manufacturing semiconductor device

Semiconductor memory devices having separation structures

Semiconductor memory device and method of manufacturing the same

3D semiconductor device and structure

Power overlay structure and reconstituted semiconductor wafer having wirebonds

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same

Advanced copper interconnects with hybrid microstructure

Method of manufacturing porous body, porous body, method of manufacturing device, device, method of manufacturing wiring structure, and wiring structure

Semiconductor memory device

Stacked multilayer structure and manufacturing method thereof

Interconnect structure with air-gaps

Copper etching integration scheme

Method for manufacturing a contact bump by thermal expansion of a patterned sacrificial layer underneath a galvanic layer

Junctionless back end of the line via contact

Electronic device and method for fabricating the same

Semiconductor memory device and method for manufacturing the same

Methods for reducing dual damascene distortion

Integrated circuit having a staggered fishbone power network

ON-CHIP VARIABLE CAPACITOR WITH GEOMETRIC CROSS-SECTION

Method for forming conductive structure using polishing process

Interconnect structure, interconnect layout structure, and manufacturing method thereof

Integrated circuit having a plurality of conductive segments

Stacked substrate structure with inter-tier interconnection

Semiconductor device having contact plug and method of forming the same

Structures to mitigate contamination on a back side of a semiconductor substrate

Techniques based on electromigration characteristics of cell interconnect

Semiconductor device and manufacturing method thereof

Self-aligned via forming to conductive line and related wiring structure

Through-memory-level via structures for a three-dimensional memory device

Through-memory-level via structures for a three-dimensional memory device

Through-memory-level via structures for a three-dimensional memory device

Semiconductor device

Semiconductor device with local interconnect structure and manufacturing method thereof

Electronic component of integrated circuitry and a method of forming a conductive via to a region of semiconductor material

Methods of forming metal pad structures over TSVS to reduce shorting of upper metal layers

Increased contact alignment tolerance for direct bonding

Three-dimensional semiconductor device

Memory device having cell over periphery structure and memory package including the same

Through-memory-level via structures for a three-dimensional memory device

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Power semiconductor device and method for manufacturing same

Cmos compatible fuse or resistor using self-aligned contacts

Semiconductor memory device and method for manufacturing the same

Voidless contact metal structures

Local interconnect structure including non-eroded contact via trenches

Semiconductor device and manufacturing method of the same

Voidless contact metal structures

Semiconductor device and method of manufacturing semiconductor device having parallel contact holes between adjacent trenches

Electronic component package and electronic device including the same

Interconnect structure and method of forming same

Semiconductor device allowing metal layer routing formed directly under metal pad

Metal line structure and method

Nanowires for pillar interconnects

Electronic device and method for fabricating the same

Structure for stacked logic performance improvement

Semiconductor device having air gap structures and method of fabricating thereof

Integrated circuit package substrate

Heterojunction semiconductor device for reducing parasitic capacitance

Electronic device and method for fabricating the same

Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same

Three-dimensional semiconductor devices having vertical structures of different lengths

Advanced copper interconnects with hybrid microstructure

Interconnect structure for semiconductor devices

METHOD FOR MANUFACTURING ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS

Active CMOS sensor array for electrochemical biomolecular detection

Semiconductor device

Semiconductor apparatus installing passive device

Power line layout structure of semiconductor device and method for forming the same

Semiconductor device and manufacturing method thereof

Hybrid airgap structure with oxide liner

Method of treating a microelectronic substrate using dilute TMAH

Chemical direct pattern plating method

Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects

Interconnect structure with misaligned metal lines coupled using different interconnect layer

Semiconductor device and method of fabricating the same

Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs

Deep trench isolation with tank contact grounding

Aware variable fill pattern generator

Buffer circuit, semiconductor integrated circuit device, oscillator, electronic apparatus, and base station

Contact window structure, pixel structure and method for manufacturing thereof

Vertical memory devices

3D NAND device with five-folded memory stack structure configuration

Semiconductor device including three-dimensional crack detection structure

Semiconductor constructions

Semiconductor memory device, structure and methods

Low resistance contact structures for trench structures

Vertical memory devices and methods of manufacturing the same

Inductor device and method of manufacturing the same

Contact via structure and fabricating method thereof

Isolation device

Semiconductor devices and methods of manufacturing the same

SRAM cell word line structure with reduced RC effects

Trench MOSFET with self-aligned body contact with spacer

ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME

Radio-frequency isolation using front side opening

Three-dimensionally integrated circuit devices including oxidation suppression layers

VERTICAL MEMORY DEVICES

Semiconductor device and manufacturing method thereof

CIRCUIT MODULE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor structure with ultra thick metal and manufacturing method thereof

Interconnection structure and manufacturing method thereof

Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

Integrated circuit with conductive line having line-ends

Semiconductor device and method of manufacturing semiconductor device

Hybrid interconnect structure and electronic device employing the same

Semiconductor memory device and method of fabricating the same

Transient voltage suppressor and manufacture method thereof

Semiconductor structure and method for forming the same

Electrically conductive interconnect including via having increased contact surface area

Interconnects through dielectric vias

Contacts for highly scaled transistors

NONVOLATILE STORAGE DEVICE, SEMICONDUCTOR ELEMENT, AND CAPACITOR

Semiconductor memory device

Three-dimensional semiconductor memory device and method for manufacturing the same

Semiconductor device including semiconductor chip, wiring, conductive material, and contact part

Surface mount high-frequency circuit

Metal on both sides with clock gated-power and signal routing underneath

Unidirectional metal on layer with ebeam

Semiconductor device

Semiconductor device

Method of forming body contact layouts for semiconductor structures

Semiconductor device and manufacturing method thereof

Semiconductor device allowing metal layer routing formed directly under metal pad

Method of preventing pattern collapse

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

Semiconductor device and method of manufacturing the same

Semiconductor device and electronic apparatus encapsulated in resin with embedded filler particles

SURFACE ENCAPSULATION FOR WAFER BONDING

Semiconductor device having air gap structures and method of fabricating thereof

Semiconductor devices having air spacers and methods of manufacturing the same

Metal interconnect structure and fabrication method thereof

Semiconductor device and fabrication method thereof

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

Methods of forming semiconductor device structures including stair step structures

Semiconductor device having a conductive via structure

Semiconductor devices including conductive lines and methods of forming the semiconductor devices

Silicon on porous silicon

Forming CMOSFET structures with different contact liners

Semiconductor device and semiconductor device manufacturing method

Interconnection structure and methods of fabrication the same

Forming CMOSFET structures with different contact liners

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Semiconductor device having channel holes

Device having an inter-layer via (ILV), and method of making same

Semiconductor device with surrounding gate transistors in a NAND circuit

Heterojunction semiconductor device for reducing parasitic capacitance

Field effect transistors and methods of forming same

Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques

Semiconductor device and a method of increasing a resistance value of an electric fuse

Semiconductor device including source/drain contact having height below gate stack

Damascene wires with top via structures

Method of manufacturing semiconductor device including copper interconnections

Desmear with metalized protective film

Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof

ESD protection device with improved bipolar gain using cutout in the body well

Semiconductor device and a method of manufacturing the same

Semiconductor devices

Semiconductor device and method for fabricating the same

Method of manufacturing a semiconductor device having groove-shaped via-hole

Electronic device

Conductive seal ring for power bus distribution

Contact Plug Extension for Bit Line Connection

Antifuse structure in via hole in interplayer dielectric

Semiconductor device with through-substrate via covered by a solder ball

SEMICONDUCTOR MEMORY DEVICE

Method of producing a semiconductor device with through-substrate via covered by a solder ball

Transmission line for 3D integrated circuit

Semiconductor device having structure for improving voltage drop and device including the same

Method of manufacturing semiconductor device and semiconductor device

VIA STRUCTURES FOR THERMAL DISSIPATION

Structure with conductive plug and method of forming the same

Necked interconnect fuse structure for integrated circuits

Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs

Integrated biosensor

Guard ring method for semiconductor devices

Semiconductor device and method of producing semiconductor device

Semiconductor interconnect structures

Thickened stress relief and power distribution layer

Semiconductor device having interconnection structure

Memory device and method of forming the same

Semiconductor package structure and method of the same

Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method

Method to reduce resistance for a copper (CU) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

SELF-ALIGNED VIA PROCESS FLOW

Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)

Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

Optimized wires for resistance or electromigration

Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture

Wiring structure and method of forming the same, and semiconductor device including the wiring structure

Optimized wires for resistance or electromigration

Interconnect structure having an etch stop layer over conductive lines

Methods and apparatuses having strings of memory cells including a metal source

Static random access memory (SRAM) device

High quality deep trench oxide

Semiconductor device allowing metal layer routing formed directly under metal pad

Superimposed transistors with auto-aligned active zone of the upper transistor

Interconnects having sealing structures to enable selective metal capping layers

Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes

Method of forming an interconnect structure for a semiconductor device

Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack

Oversized contacts and vias in layout defined by linearly constrained topology

Integrated circuit with elongated coupling

Contacts to semiconductor substrate and methods of forming same

Nonvolatile memory device and method for fabricating the same

Via formation using sidewall image transfer process to define lateral dimension

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor structure and fabrication method thereof

TEST PATTERN STRUCTURE FOR MONITORING SEMICONDUCTOR FABRICATION PROCESS

Thin film transistor and manufacturing method thereof

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure

Semiconductor lead frame, semiconductor package, and manufacturing method thereof

Wiring board, semiconductor device, and manufacturing methods thereof

Radio frequency isolation using substrate opening

Radio frequency isolation cavity formation using sacrificial material

Substrate opening formation in semiconductor devices

Cavity formation in semiconductor devices

Semiconductor device and method for manufacturing the same