208247 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes Tunnel injectors
DOUBLE GATE TRANSISTOR DEVICE AND METHOD OF OPERATING
#2Tunneling Enabled Feedback FET
#3MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
#4Method of fabricating semiconductor device
#5Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#6Method for manufacturing semiconductor device
#7Field-effect transistor structure and fabrication method
#8MIS contact structure with metal oxide conductor
#9Tunneling field effect transistor
#10Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#11Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#12Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#13Graphene device, methods of manufacturing and operating the same, and electronic apparatus including the graphene device
#14MIS contact structure with metal oxide conductor
#15Double gate transistor device and method of operating
#16Energy-filtered cold electron devices and methods
#17Semiconductor device and manufacturing method thereof
#18Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#19Semiconductor device and method of fabricating the same
#20Energy-filtered cold electron devices and methods
#21InN tunnel junction contacts for P-channel GaN
#22MIS contact structure with metal oxide conductor
#23Tunneling Junction Transistor
#24Vertical transistor gated diode
#25Energy-filtered cold electron devices and methods
#26Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#27TUNNEL FINFET WITH SELF-ALIGNED GATE
#28Homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications
#29Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#30Tunnel field-effect transistor (TFET) with lateral oxidation
#31Quantum box device comprising dopants located in a thin semiconductor layer
#32MIS contact structure with metal oxide conductor
#33Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#34Surface area and Schottky barrier height engineering for contact trench epitaxy
#35Surface area and Schottky barrier height engineering for contact trench epitaxy
#36Graphene double-barrier resonant tunneling device
#37Energy-filtered cold electron devices and methods
#38Double gate transistor device and method of operating
#39Junction interlayer dielectric for reducing leakage current in semiconductor devices
#40SBFET transistor and corresponding fabrication process
#41Insulated gate field effect transistor having passivated schottky barriers to the channel
#42Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs
#43Tunnel field effect transistors
#44Group III-nitride compound heterojunction tunnel field-effect transistors and methods for making the same
#45Systems and methods for filtering and computation using tunneling transistors
#46Energy-filtered cold electron devices and methods
#47Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#48Magnetoresistive element and spin-transport element
#49Transistor with MIS connections and fabricating process
#50Tunnel thin film transistor with hetero-junction structure
#51Junction interlayer dielectric for reducing leakage current in semiconductor devices
#52Devices for utilizing symFETs for low-power information processing
#53Tunnel field effect transistor (TFET) with lateral oxidation
#54Transistor and method for forming the same
#55Layered structure of a P-TFET
#56Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device
#57Semiconductor device contacts
#58Semiconductor device and method of manufacturing the same
#59Graphene device, methods of manufacturing and operating the same, and electronic apparatus including the graphene device
#60Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
#61Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#62Compact memory structure including tunneling diode
#63Tunneling field effect transistor with new structure and preparation method thereof
#64Accumulation-mode MOSFET and driving method thereof
#65Field effect semiconductor device
#66Gate tunable tunnel diode
#67Tunnel field-effect transistors with a gate-swing broken-gap heterostructure
#68Thin film transistor and method for manufacturing same
#69Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
#70Tunnel field-effect transistors with a gate-swing broken-gap heterostructure
#71Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
#72Field-effect transistor with two-dimensional channel realized with lateral heterostructures based on hybridized graphene
#73Graphene devices and methods of fabricating the same
#74Insulated gate field effect transistor having passivated schottky barriers to the channel
#75Tunnel junction field effect transistors having self-aligned source and gate electrodes and methods of forming the same
#76TFET with nanowire source
#77Semiconductor device and method for manufacturing the same
#78Tunneling field-effect transistor including graphene channel
#79Gate tunable tunnel diode
#80Gate tunable tunnel diode
#81Method for manufacturing a tunneling field effect transistor with a U-shaped channel
#82Insulated gate field effect transistor having passivated schottky barriers to the channel
#83Semiconductor device and manufacturing method thereof
#84Tunnel field effect transistor (TFET) with lateral oxidation
#85GERMANIUM-BASED NMOS DEVICE AND METHOD FOR FABRICATING THE SAME
#86Graphene switching device having tunable barrier
#87Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
#88Graphene base transistor having compositionally-graded collector barrier layer
#89FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR
#90Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#91Semiconductor switching device employing a quantum dot structure
#92Semiconductor device and method of manufacturing same
#93Semiconductor device contacts
#94Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
#95DYNAMIC SCHOTTKY BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE
#96LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
#97Spin MOSFET and reconfigurable logic circuit
#98Apparatus, system, and method for tunneling MOSFETs using self-aligned heterostructure source and isolated drain
#99TFET with nanowire source
#100TRANSISTOR AND MANUFACTURING METHOD THEREOF
#101Insulated gate field effect transistor having passivated schottky barriers to the channel
#102Semiconductor device and method of manufacturing the same
#103Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#104Tunnel field effect transistors
#105Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
#106Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
#107Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current
#108Semiconductor device
#109Field effect transistor having graphene channel layer
#110Spin MOSFET and reconfigurable logic circuit
#111Semiconductor switching device employing a quantum dot structure
#112Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
#113Dynamic Schottky barrier MOSFET device and method of manufacture
#114Spin injector
#115Metal-oxide-semiconductor device including an energy filter
#116Metal-oxide-semiconductor device including an energy filter
#117SPIN FILTER SPINTRONIC DEVICES
#118Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#119RESISTANCE-SWITCHING OXIDE THIN FILM DEVICES
#120Low contact resistance ohmic contact for a high electron mobility transistor and fabrication method thereof
#121Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
#122Integrated Circuit with a Transistor Structure Element
#123Non-volatile resistance-switching oxide thin film devices
#124Resistance-switching memory based on semiconductor composition of perovskite conductor doped perovskite insulator
#125Insulated gate field effect transistor having passivated schottky barriers to the channel
#126Dynamic Schottky barrier MOSFET device and method of manufacture
#127Heterjunction bipolar transistor with tunnelling mis emitter junction
#128Resonant tunneling device using metal oxide semiconductor processing
#129Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
#130Integrated semiconductor storage with at least a storage cell and procedure
#131Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#132Dynamic schottky barrier MOSFET device and method of manufacture
#133Doping method and semiconductor device using the same
#134Discontinuous dielectric interface for bipolar transistors
#135Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
#136MISFET
#137Integrated semiconductor storage with at least a storage cell and procedure
#138Localized tunneling enhancement for semiconductor devices
#139Vertical transistor gated diode
#140Tunneling transistor suitable for low voltage operation