208274 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed; Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices Doping structures, e.g. doping superlattices, nipi superlattices
A VERTICAL HEMT, AN ELECTRICAL CIRCUIT, AND A METHOD FOR PRODUCING A VERTICAL HEMT
#2TIN AS NUCLEAR SPIN QUBIT IN SILICON
#3SURFACE-DOPED CHANNELS FOR THRESHOLD VOLTAGE MODULATION
#4BUFFER STRUCTURE WITH INTERLAYER BUFFER LAYERS FOR HIGH VOLTAGE DEVICE
#5SEMICONDUCTOR DEVICE
#6Fabricating Method of Semiconductor Device
#7NITRIDE SEMICONDUCTOR BUFFER STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
#8GALLIUM NITRIDE POWER TRANSISTOR
#9NITRIDE SEMICONDUCTOR AND SEMICONDUCTOR DEVICE
#10Cartridge for inspection
#11SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME
#12Epitaxial structure for high-electron-mobility transistor and method for manufacturing the same
#13POWER SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#14SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#15SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE PROVIDING METAL WORK FUNCTION TUNING
#16Surface-Doped Channels for Threshold Voltage Modulation
#17SUPERLATTICE STRUCTURE
#18Semiconductor device and method for manufacturing the same
#19Type III-V semiconductor device with improved leakage
#20Semiconductor device and fabricating method thereof
#21Stacked, high-blocking InGaAs semiconductor power diode
#22Reprogrammable quantum processor architecture incorporating quantum error correction
#23Stacked high barrier III-V power semiconductor diode
#24Semiconductor device
#25Conformal oxidation for gate all around nanosheet I/O device
#26Epitaxial structure having super-lattice laminates
#27CHARGE-TRAPPING LAYERS FOR III-V SEMICONDUCTOR DEVICES
#28Method for forming super-junction corner and termination structure with graded sidewalls
#29Semiconductor crystal substrate, infrared detector, and method for producing semiconductor crystal substrate
#30Reprogrammable quantum processor architecture incorporating quantum error correction
#31Transistor with strained superlattice as source/drain region
#32Semiconductor structure comprising p-type N-face GAN-based semiconductor layer and manufacturing method for the same
#33Semiconductor structure and manufacturing method for the semiconductor structure
#34Semiconductor structure having sets of III-V compound layers and method of forming
#35Semiconductor structure having sets of III-V compound layers and method of forming
#36Semiconductor device
#37Epitaxial structure for high-electron-mobility transistor and method for manufacturing the same
#38Stacked high barrier III-V power semiconductor diode
#39Stacked, high-blocking InGaAs semiconductor power diode
#40Super-junction corner and termination structure with graded sidewalls
#41Semiconductor controlled quantum swap interaction gate
#42Semiconductor controlled quantum interaction gates
#43Classic-quantum injection interface device
#44Semiconductor controlled quantum Pauli interaction gate
#45FinFET quantum structures utilizing quantum particle tunneling through oxide
#46Finfet quantum structures utilizing quantum particle tunneling through local depleted well
#47Reprogrammable quantum processor architecture incorporating calibration loops
#48Reprogrammable quantum processor architecture
#49Quantum structure incorporating electric and magnetic field control
#50Quantum structure incorporating phi angle control
#51Quantum structure incorporating theta angle control
#52Quantum-classic detection interface device
#53Planar quantum structures utilizing quantum particle tunneling through local depleted well
#54Super-junction corner and termination structure with improved breakdown and robustness
#55Nitride semiconductor substrate, manufacturing method therefor, and semiconductor device
#56Zero capacitance electrostatic discharge device
#57Semiconductor crystal substrate, infrared detector, and method for producing semiconductor crystal substrate
#58Power semiconductor device having a field electrode
#59Forming a superjunction transistor device
#60Semiconductor device and a manufacturing method therefor
#61Gate walls for quantum dot devices
#62Semiconductor structure having sets of III-V compound layers and method of forming
#63Polarization-doped enhancement mode HEMT
#64Quantum doping method and use in fabrication of nanoscale electronic devices
#65Bipolar transistor with superjunction structure
#66High density nanosheet diodes
#67Group III-V device structure with variable impurity concentration
#68FinFETs with strained well regions
#69Low-voltage charge-coupled devices with a heterostructure charge-storage well
#70Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
#71Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
#72Semiconductor device including resonant tunneling diode structure having a superlattice
#73Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
#74Super-junction schottky diode
#75Power semiconductor device having a field electrode
#76Semiconductor device and manufacturing method therefor
#77Method of manufacturing a super junction semiconductor device and super junction semiconductor device
#78FinFETs with strained well regions
#79FinFETs with strained well regions
#80Extreme high mobility CMOS logic
#81Methods of making multichannel devices with improved performance
#82Semiconductor device having a super junction structure
#83High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
#84SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
#85Method of forming an integrated circuit with heat-mitigating diamond-filled channels
#86Method of forming an integrated circuit with heat-mitigating diamond-filled channels
#87Group III-V device structure having a selectively reduced impurity concentration
#88Method and apparatus providing improved thermal conductivity of strain relaxed buffer
#89Bipolar transistor with superjunction structure
#90Silicon carbide semiconductor device and method for producing the same
#91Method of Manufacturing a Semiconductor Device by Plasma Doping
#92Tunable voltage margin access diodes
#93SEMICONDUCTOR DEVICE
#94Horizontal gate all around device isolation
#95FinFETs with strained well regions
#96Method and apparatus providing improved thermal conductivity of strain relaxed buffer
#97SEMICONDUCTOR DEVICE
#98Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
#99Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
#100Tunable voltage margin access diodes
#101GaO-based semiconductor element
#102SEMICONDUCTOR DEVICE
#103Tunable voltage margin access diodes
#104Tunable voltage margin access diodes
#105FinFETs with strained well regions
#106Power MOS transistor and manufacturing method therefor
#107Dual trench-gate IGBT structure
#108Nitride semiconductor wafer, nitride semiconductor element, and method for manufacturing nitride semiconductor wafer
#109High electron mobility transistor
#110High electron mobility transistor
#111Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device
#112Silicene material layer and electronic device having the same
#113Zero-Dimensional Electron Devices and Methods of Fabricating the Same
#114NITRIDE BASED SEMICONDUCTOR DEVICE
#115Group III-V device with a selectively modified impurity concentration
#116Semiconductor structure having sets of III-V compound layers and method of forming the same
#117Nitride semiconductor wafer, nitride semiconductor element, and method for manufacturing nitride semiconductor wafer
#118Semiconductor device including at least one type of deep-level dopant
#119Transistor having graphene base
#120Dual trench-gate IGBT structure
#121Nitride semiconductor wafer, nitride semiconductor element, and method for manufacturing nitride semiconductor wafer
#122Group III-V device with a selectively modified impurity concentration
#123Group III-V device with a selectively reduced impurity concentration
#124Semiconductor structure having sets of III-V compound layers and method of forming the same
#125Method for forming an optical modulator
#126Diamond sensors, detectors, and quantum devices
#127Semiconductor Device and Method of Manufacturing a Semiconductor Device
#128Semiconductor device including first and second semiconductor materials
#129Group III-V device structure having a selectively reduced impurity concentration
#130Controlled Doping in III-V Materials
#131Extreme high mobility CMOS logic
#132Transistor having graphene base
#133NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#134Method for dopant calibration of delta doped multilayered structure
#135Extreme high mobility CMOS logic
#136Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed
#137Semiconductor superjunction device
#138Method for forming a doping superlattice using a laser
#139Low doped layer for nitride-based semiconductor device
#140P-type diamond gate-GaN heterojunction FET structure
#141Quantum doping method and use in fabrication of nanoscale electronic devices