208275 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed; Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE
#2METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE
#3DMOS DEVICES INCLUDING A SUPERLATTICE AND FIELD PLATE FOR DRIFT REGION DIFFUSION
#4Method for making nanostructure transistors with source/drain trench contact liners
#5Method for making nanostructure transistors with flush source/drain dopant blocking structures including a superlattice
#6METHOD FOR MAKING RADIO FREQUENCY SILICON-ON-INSULATOR (RFSOI) STRUCTURE INCLUDING A SUPERLATTICE
#7Semiconductor device-including source and drain regions and superlattice pattern having a pillar shape
#8Superlattice structure including two-dimensional material and device including the superlattice structure
#9NANORIBBON-BASED QUANTUM DOT DEVICES
#10Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
#11Semiconductor epitaxy structure
#12Lateral bipolar transistor structure with superlattice layer and method to form same
#13Semiconductor device including superlattice pattern
#14Superlattice structure including two-dimensional material and device including the superlattice structure
#15Quantum well stacks for quantum dot devices
#16Semiconductor device including superlattice pattern
#17Method for forming super-junction corner and termination structure with graded sidewalls
#182D crystal hetero-structures and manufacturing methods thereof
#19Quantum well stacks for quantum dot devices
#20Hexagonal arrays for quantum dot devices
#21Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)
#22Super-junction corner and termination structure with graded sidewalls
#23Semiconductor process for quantum structures with staircase active well
#24Stretchable form of single crystal silicon for high performance electronics on rubber substrates
#25Superlattice structure including two-dimensional material and device including the superlattice structure
#26Super-junction corner and termination structure with improved breakdown and robustness
#27Group III-N nanowire transistors
#28Power semiconductor device having a field electrode
#29Forming a superjunction transistor device
#30Semiconductor device and a manufacturing method therefor
#31Stress relieving semiconductor layer
#32Semiconductor device structure having carrier-trapping layers with different grain sizes
#33Polarization-doped enhancement mode HEMT
#342D crystal hetero-structures and manufacturing methods thereof
#35Super-junction schottky diode
#36Power semiconductor device having a field electrode
#37Semiconductor device and manufacturing method therefor
#38Heterojunction bipolar transistor
#39Method of manufacturing a super junction semiconductor device and super junction semiconductor device
#40Group III-N nanowire transistors
#41Stress relieving semiconductor layer
#42METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR
#43THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
#44Silicon carbide semiconductor device and method for producing the same
#45Method of Manufacturing a Semiconductor Device by Plasma Doping
#46Horizontal gate all around device isolation
#47Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
#48Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
#49Method of manufacturing a semiconductor device including a gate electrode on a protruding group III-V material layer
#50Group III-N nanowire transistors
#51Stress relieving semiconductor layer
#52Stress relieving semiconductor layer
#53Quantum dot channel (QDC) quantum dot gate transistors, memories and other devices
#54Method to fabricate quantum dot field-effect transistors without bias-stress effect
#55SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SIGE/SI FIN STRUCTURE
#56Semiconductor device including superlattice SiGe/Si fin structure
#57FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS
#58Stretchable form of single crystal silicon for high performance electronics on rubber substrates
#59Solid state cloaking for electrical charge carrier mobility control
#60Epitaxial growth of in-plane nanowires and nanowire devices
#61Semiconductor Device and Method of Manufacturing a Semiconductor Device
#62Semiconductor device including a gate electrode on a protruding group III-V material layer and method of manufacturing the semiconductor device
#63Epitaxial growth of in-plane nanowires and nanowire devices
#64SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND DOPANT DIFFUSION RETARDING IMPLANTS AND RELATED METHODS
#65Stretchable form of single crystal silicon for high performance electronics on rubber substrates
#66Quantum coherent switch utilizing commensurate nanoelectrode and charge density periodicities
#67Method for producing planar transporting resonance heterostructures
#68Semiconductor device with a vertical MOSFET including a superlattice and related methods
#69Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
#70Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
#71Stretchable form of single crystal silicon for high performance electronics on rubber substrates
#72Method of production of nano particle dispersed composite material
#73Quantum coherent switch utilizing commensurate nanoelectrode and charge density periodicities
#74Semiconductor device with a buried junction layer having an interspersed pattern of doped and counter-doped materials
#75Power schottky diodes having local current spreading layers and methods of forming such devices