208282 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group , e.g. alloys in different semiconductor regions, e.g. heterojunctions
HETEROGENEOUS METAL LINE COMPOSITIONS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#2SEMICONDUCTOR STRUCTURE
#3INTEGRATED CIRCUIT
#4CONTACT OVER ACTIVE GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#5HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
#6FETS and Methods of Forming FETS
#7SEMICONDUCTOR DEVICE
#8REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS
#9NOISE TRANSISTOR
#10HIGH FREQUENCY HETEROJUNCTION BIPOLAR TRANSISTOR DEVICES
#11CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS
#12SEMICONDUCTOR DEVICE
#13SEMICONDUCTOR DEVICE HAVING A SHAPED EPITAXIAL REGION WITH SHAPING SECTION
#14SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#15SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#16METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
#17SEMICONDUCTOR DEVICE STRUCTURE HAVING GATE DIELECTRIC LAYER
#18Conductive Features of Semiconductor Devices and Methods of Forming the Same
#19FinFET Device With High-K Metal Gate Stack
#20STRESS-INDUCING SILICON LINER IN SEMICONDUCTOR DEVICES
#21METHOD FOR FORMING SOURCE/DRAIN CONTACTS
#22SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#23SEMICONDUCTOR DEVICES
#24SEMICONDUCTOR DEVICE
#25SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
#26COMPLEMENTARY BIPOLAR JUNCTION TRANSISTOR
#27SEMICONDUCTOR DEVICE STRUCTURE WITH CAP LAYER
#28WIDE BANDGAP MATERIAL IN DRIFT WELL OF SEMICONDUCTOR DEVICE
#29STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR
#30RAISED SOURCE/DRAIN TRANSISTOR
#31METHODS OF FORMING GATE-ALL-AROUND (GAA) DEVICES
#32METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
#33Source/Drain Feature to Contact Interfaces
#34REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE AND METHOD OF FABRICATION THEREFOR
#35LIGHTLY-DOPED CHANNEL EXTENSIONS
#36GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH INNER SPACERS AND METHODS
#37Epitaxial wafer, Method of manufacturing the epitaxial wafer, and Method of manufacturing a semiconductor device using the epitaxial wafer
#38GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#39MULTI-LAYER CHANNEL STRUCTURES AND METHODS OF FABRICATING THE SAME IN FIELD-EFFECT TRANSISTORS
#40METHOD FOR FORMING SOURCE/DRAIN CONTACTS
#41MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
#42STACKED GATE-ALL-AROUND FINFET AND METHOD FORMING THE SAME
#43ROUNDED NANORIBBONS WITH REGROWN CAPS
#44METHOD OF FORMING SOURCE/DRAIN EPITAXIAL STACKS
#45SIGE HBT AND METHODS OF MANUFACTURING THE SAME
#46SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#47Tunneling Field Effect Transistor and Manufacturing Method Thereof, Display Panel and Display Apparatus
#48LATERAL BIPOLAR TRANSISTORS
#49SELF-ALIGNED INTERCONNECT WITH PROTECTION LAYER
#50INTEGRATE-AND-FIRE NEURON CIRCUIT AND OPERATION METHOD THEREOF
#51SEMICONDUCTOR DEVICE
#52Fin smoothing and integrated circuit structures resulting therefrom
#53SEMICONDUCTOR DEVICE HAVING ANISOTROPIC LAYER
#54Integrated circuit with a Fin and gate structure and method making the same
#55SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES
#56Semiconductor device
#57MECHANISMS FOR GROWING EPITAXY STRUCTURE OF FINFET DEVICE
#58STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
#59Lateral fin static induction transistor
#60Semiconductor device
#61METHOD OF MANUFACTURING A SILICON BIPOLAR JUNCTION TRANSISTOR, AND A BJT
#62SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER LAYER
#63SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
#64RF DEVICES WITH NANOTUBE PARTICLES FOR ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME
#65SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH
#66Method of Forming a Source/Drain
#67SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS
#68METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS
#69SEMICONDUCTOR DEVICE HAVING ASYMMETRICAL SOURCE/DRAIN
#70Method to induce strain in finFET channels from an adjacent region
#71NANOSHEET SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#72Semiconductor device with helmet structure between two semiconductor fins
#73DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#74Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
#75POWER REDUCTION IN FINFET STRUCTURES
#76Trench contact structures for advanced integrated circuit structure fabrication
#77Semiconductor device having a liner layer and method of fabricating the same
#78Fin field-effect transistor device having contact plugs with re-entrant profile
#79Semiconductor device having doped epitaxial region and its methods of fabrication
#80Integrated circuit structures having germanium-based channels
#81Different Isolation Liners for Different Type FinFETs and Associated Isolation Feature Fabrication
#82Forming nanosheet transistor using sacrificial spacer and inner spacers
#83FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
#84SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE
#85Multi-Gate Device And Method Of Fabrication Thereof
#86FLEXIBLE MERGE SCHEME FOR SOURCE/DRAIN EPITAXY REGIONS
#87METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMED
#88Conformal transfer doping method for Fin-like field effect transistor
#89METHOD FOR FORMING SEMICONDUCTOR DEVICE
#90VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
#91SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES
#92FIELD EFFECT TRANSISTORS WITH DUAL SILICIDE CONTACT STRUCTURES
#93Gate-all-around integrated circuit structures having insulator fin on insulator substrate
#94GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES
#95Semiconductor device including epitaxial region
#96SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#97ACTIVE AREA SALICIDATION FOR NMOS AND PMOS DEVICES
#98METHOD FOR PRODUCING A PRETREATED COMPOSITE SUBSTRATE, AND PRETREATED COMPOSITE SUBSTRATE
#99HETEROGENEOUS METAL LINE COMPOSITIONS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#100Semiconductor Device and Method
#101Semiconductor devices with dissimlar materials and methods
#102Semiconductor devices and methods of manufacturing semiconductor devices
#103Gate structure and method with enhanced gate contact and threshold voltage
#104Diode
#105Dopant Concentration Boost in Epitaxially Formed Material
#106SEMICONDUCTOR DEVICE
#107Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
#108Semiconductor device including a gate-all-around field effect transistor
#109HETEROSTRUCTURE CHANNEL LAYER FOR SEMICONDUCTOR DEVICES
#110Horizontal Current Bipolar Transistor with Silicon-Germanium base
#111IC including standard cells and SRAM cells
#112Semiconductor device with self-aligned wavy contact profile and method of forming the same
#113METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE
#114SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES
#115Isolation Structures Of Semiconductor Devices
#116SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
#117FINFETS having step sided contact plugs and methods of manufacturing the same
#118SEMICONDUCTOR DEVICE
#119ULTRA-THIN FIN STRUCTURE AND METHOD OF FABRICATING THE SAME
#120DOPING PROFILE FOR STRAINED SOURCE/DRAIN REGION
#121SEMICONDUCTOR DEVICE
#122Semiconductor device, method of manufacturing the same and electronic device including the device
#123Semiconductor device and manufacturing method thereof
#124Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
#125Method for forming source/drain contacts
#126Method of forming finFET with low-dielectric-constant gate electrode spacers
#127Semiconductor device and manufacturing method thereof
#128Fin Field Effect Transistor (FinFET) Device and Method for Forming the Same
#129Strained-channel fin FETs
#130Semiconductor structure
#131Methods for increasing germanium concentration of surfaces of a silicon germanium portion of a Fin and resulting semiconductor devices
#132Semiconductor device including source/drain having sidewalls with convex and concave portions
#133FETs and methods of forming FETs
#134Semiconductor device with source/drain contact
#135GATE STRUCTURE AND METHOD
#136Semiconductor device and method of manufacturing the same
#137Semiconductor device with source/drain contact formed using bottom-up deposition
#138Method of fabricating Fin-type field-effect transistor device having substrate with heavy doped and light doped regions
#139SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#140ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION
#141HIGH DOSE IMPLANTATION FOR ULTRATHIN SEMICONDUCTOR-ON-INSULATOR SUBSTRATES
#142FABRICATION METHOD FOR SEMICONDUCTOR STRUCTURE
#143Heterojunction bipolar transistor with buried trap rich isolation region
#144Method of manufacturing a semiconductor device and a semiconductor device
#145Method for epitaxial growth and device
#146Fin smoothing and integrated circuit structures resulting therefrom
#147Lateral bipolar junction transistors including a graded silicon-germanium intrinsic base
#148Structure of Semiconductor Device Structure Having Fins
#149SEMICONDUCTOR DEVICE WITH CAP ELEMENT
#150Structure And Method For Mosfet Device
#151Semiconductor device structure with barrier layer
#152Semiconductor device and manufacturing method thereof
#153SEMICONDUCTOR DEVICE WITH DIELECTRIC SPACER LINER ON SOURCE/DRAIN CONTACT
#154Field effect transistor with controllable resistance
#155MANUFACTURING METHOD FOR HIGH-VOLTAGE TRANSISTOR
#156Trench contact structures for advanced integrated circuit structure fabrication
#157SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
#158Semiconductor device and manufacturing method thereof
#159Structure and formation method of fin-like field effect transistor
#160Semiconductor device and manufacturing method thereof
#161Structure of a fin field effect transistor (FinFET) comprising epitaxial structures
#162Semiconductor devices and method of manufacturing the same
#163Semiconductor device with self-aligned wavy contact profile and method of forming the same
#164Semiconductor device
#165Semiconductor device structure with inner spacer layer and method for forming the same
#166Confined epitaxial regions for semiconductor devices
#167Bipolar junction device
#168TRENCH ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#169Semiconductor devices
#170GRAPHENE STRUCTURE AND METHOD OF FORMING GRAPHENE STRUCTURE
#171METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STRUCTURES
#172Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class
#173Semiconductor devices having different numbers of stacked channels in different regions
#174Transistor with monocrystalline base structures
#175Enhanced channel strain to reduce contact resistance in NMOS FET devices
#176JUMPER GATE FOR ADVANCED INTEGRATED CIRCUIT STRUCTURES
#177SUPER-JUNCTION SEMICONDUCTOR DEVICE WITH ENLARGED PROCESS WINDOW FOR DESIRABLE BREAKDOWN VOLTAGE
#178CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL
#179GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOLATION
#180Semiconductor device and method for fabricating the same
#181Method to induce strain in FINFET channels from an adjacent region
#182Contact over active gate structures for advanced integrated circuit structure fabrication
#183FORMATION OF GATE SPACERS FOR STRAINED PMOS GATE-ALL-AROUND TRANSISTOR STRUCTURES
#184GATE LINE PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#185FIN PATTERNING FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#186Semiconductor device
#187Low-resistance contact plugs and method forming same
#188METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE
#189Semiconductor device structure with cap layer
#190Self-aligned epitaxy layer
#191Hybrid scheme for improved performance for P-type and N-type FinFETs
#192Heterogeneous metal line compositions for advanced integrated circuit structure fabrication
#193Bipolar junction transistors with duplicated terminals
#194Semiconductor devices with dissimlar materials and methods
#195Backside electrical contacts to buried power rails
#196Method of manufacturing a semiconductor device and a semiconductor device
#197Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
#198GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING VERTICALLY DISCRETE SOURCE OR DRAIN STRUCTURES
#199Bipolar junction transistors with a nanosheet intrinsic base
#200Fin-based lateral bipolar junction transistor and method
#201Lateral bipolar transistors
#202Lateral heterojunction bipolar transistor with emitter and/or collector regrown from substrate and method
#203Semiconductor Device and Method of Direct Wafer Bonding Between Semiconductor Layer Containing Similar WBG Materials
#204Annular bipolar transistors
#205Metal-insensitive epitaxy formation
#206Finfet Device Having A Channel Defined In A Diamond-Like Shape Semiconductor Structure
#207Semiconductor device and manufacturing method thereof
#208Germanium-Silicon-Tin (GeSiSn) Heterojunction Bipolar Transistor Devices
#209Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
#210Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
#211Methods of forming dislocation enhanced strain in NMOS and PMOS structures
#212GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING UNDERLYING DOPANT-DIFFUSION BLOCKING LAYERS
#213SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
#214Integrated circuit structures having germanium-based channels
#215PMOSFET SOURCE DRAIN
#216Mechanisms for growing epitaxy structure of finFET device
#217Semiconductor device and method
#218Conformal transfer doping method for fin-like field effect transistor
#219Interfacial layer between fin and source/drain region
#220IC including standard cells and SRAM cells
#221Electrical devices making use of counterdoped junctions
#222Method of forming source/drain epitaxial stacks
#223METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
#224Stress-inducing silicon liner in semiconductor devices
#225Supportive layer in source/drains of FinFET devices
#226Three-dimensional memory device having pocket structure in memory string and method for forming the same
#227Semiconductor device
#228Method of manufacturing a semiconductor device and semiconductor wafer
#229Lightly-doped channel extensions
#230Method of fabricating a multi-gate device
#231Semiconductor device having tipless epitaxial source/drain regions
#232FinFET Structures and Methods of Forming the Same
#233Semiconductor devices and methods of manufacturing thereof
#234Gate-all-around integrated circuit structures having dual nanoribbon channel structures
#235Method for manufacturing semiconductor structure
#236Semiconductor device with source/drain epitaxial layer
#237Two dimension material fin sidewall
#238Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#239Semiconductor Device and Method
#240METHOD OF FORMING DEVICES WITH STRAINED SOURCE/DRAIN STRUCTURES
#241Methods for forming recesses in source/drain regions and devices formed thereof
#242Strained Channel Field Effect Transistor
#243Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith
#244Method for forming semiconductor device with helmet structure between two semiconductor fins
#245METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#246STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR
#247EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
#248Semiconductor device having a liner layer and method of fabricating the same
#249Semiconductor Device and Method of Manufacture
#250Fin field-effect transistor device having contact plugs with re-entrant profile
#251Plugs for interconnect lines for advanced integrated circuit structure fabrication
#252Gate etch back with reduced loading effect
#253Semiconductor device including epitaxial region
#254Semiconductor device and method
#255Method of manufacturing a heterostructure or a stacked semiconductor structure having a silicon-germanium interface
#256Silicon on insulator device with partially recessed gate
#257Semiconductor devices and method of manufacturing the same
#258Semiconductor method and device
#259Devices including gate spacer with gap or void and methods of forming the same
#260METHOD FOR DEPOSITING A GROUP IV SEMICONDUCTOR AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
#261Diode
#262Semiconductor device structure with barrier layer
#263SOURCE/DRAIN EPI STRUCTURE FOR DEVICE BOOST
#264Semiconductor Device and Method
#265Semiconductor device
#266Method of forming FinFET with low-dielectric-constant gate electrode spacers
#267Semiconductor device structure with spacer
#268Integrated circuits having source/drain structure and method of making
#269Methods of manufacture of advanced wafer bonded heterojunction bipolar transistors
#270Semiconductor structure
#271Fin-based device having an isolation gate interfacing with a source/drain
#272Nanosheet semiconductor device and method for manufacturing the same
#273Method of forming source/drain regions with expanded widths
#274HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMCONDUCTOR MATERIAL IN SILICON RECESS
#275TRANSISTOR DEVICES HAVING SOURCE/DRAIN STRUCTURE CONFIGURED WITH HIGH GERMANIUM CONTENT PORTION
#276Fin field-effect transistor device and method
#277Semiconductor device including metal-2 dimensional material-semiconductor contact
#278Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof
#279Semiconductor Device and Method for Manufacturing the Same
#280Semiconductor device and method for fabricating the same
#281Method of manufacturing a semiconductor device and a semiconductor device
#282Gate-all-around integrated circuit structures having insulator FIN on insulator substrate
#283Semiconductor device having capping layers with different germanium concentrations over an active pattern
#284Apparatuses including passing word lines comprising a band offset material, and related methods and systems
#285Semiconductor device having asymmetrical source/drain
#286Methods of forming dislocation enhanced strain in NMOS and PMOS structures
#287Stack, electronic device, and method for manufacturing stack
#288Memory array and memory device
#289Semiconductor device
#290Semiconductor device structure with etch stop layer for reducing RC delay
#291Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
#292Semiconductor device and manufacturing method thereof
#293Bipolar junction device
#294Semiconductor memory device with high electron mobility channels and method of manufacturing the same
#295Structure and method for SRAM FinFET device having an oxide feature
#296Field effect transistor contact with reduced contact resistance
#297Semiconductor structure and manufacturing method thereof
#298Semiconductor devices and methods of manufacturing semiconductor devices
#299INTEGRATED CIRCUIT STRUCTURES HAVING GESNB SOURCE OR DRAIN STRUCTURES
#300Semiconductor device and manufacturing method thereof