Method for epitaxial growth and device

Field effect transistors with dual silicide contact structures

Contact resistance reduction in nanosheet device structure

Semiconductor device

Method for fabricating a strained structure and structure formed

Semiconductor device including a Fin-FET and method of manufacturing the same

Isolation structures of semiconductor devices

Patterned silicon substrate-silicon germanium, thin film composite structure and preparation methods and application thereof

Spacer structures for semiconductor devices

Semiconductor device

Method of manufacturing semiconductor device

Threshold adjustment for quantum dot array devices with metal source and drain

QUANTUM COMPUTING ASSEMBLIES

Lightly-doped channel extensions

Semiconductor devices and methods of manufacturing the same

Method of forming a source/drain

Heterojunction bipolar transistor with buried trap rich isolation region

Methods of forming semiconductor devices having stressed active regions therein

FinFETs having step sided contact plugs and methods of manufacturing the same

Complementary bipolar junction transistor

REDUCING BAND-TO-BAND TUNNELING IN SEMICONDUCTOR DEVICES

Bipolar junction device

Contact resistance reduction employing germanium overlayer pre-contact metalization

Semiconductor device with self-aligned wavy contact profile and method of forming the same

Structure of high-voltage transistor and method for fabricating the same

HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF MAKING THE SAME

Semiconductor devices with dissimlar materials and methods

Semiconductor devices and methods of manufacturing the same

Vertical transport field-effect transistors having germanium channel surfaces

Ultra-thin fin structure and method of fabricating the same

Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same

Bipolar junction transistor (BJT) comprising a multilayer base dielectric film

Heterojunction bipolar transistor with a silicon oxide layer on a silicon germanium base

Integrated circuit devices and methods of manufacturing the same

Method for germanium enrichment around the channel of a transistor

Method of manufacturing a semiconductor device and a semiconductor device

Methods of forming dislocation enhanced strain in NMOS and PMOS structures

Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

Power reduction in finFET structures

Semiconductor device

Stacked field effect transistor with wrap-around contacts

Passivated and faceted for fin field effect transistor

Semiconductor device structure with inner spacer layer

Horizontal current bipolar transistor with silicon-germanium base

Source/drain EPI structure for device boost

Semiconductor device and method for fabricating the same

Method for preparating SiC ohmic contact with low specific contact resistivity

Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion

Semiconductor device

Self-organized quantum dot manufacturing method and quantum dot semiconductor structure

Semiconductor devices and methods of manufacturing thereof

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Strained semiconductor FET devices with epitaxial quality improvement

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON GATE DIELECTRIC LAYER

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON INSULATOR

Field effect transistor with controllable resistance

Forming nanosheet transistor using sacrificial spacer and inner spacers

Method of fabricating a source/drain recess in a semiconductor device

Nanopore structures

Gate structure and method with enhanced gate contact and threshold voltage

Gate-all-around (GAA) method and devices

Semiconductor device and method of manufacture

Quantum dot devices with trenched substrates

APPARATUSES INCLUDING MEMORY CELLS AND RELATED METHODS

Semiconductor arrangement and method of manufacture

Spin to photon transducer

Semiconductor device and method of manufacturing the same

Semiconductor device including a field effect transistor and method of fabricating the same

Semiconductor device and manufacturing method thereof

Semiconductor device and method

Different isolation liners for different type FinFETs and associated isolation feature fabrication

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Method for forming a semiconductor device and a semiconductor device

Fin field-effect transistor device having contact plugs with re-entrant profile

Semiconductor device having a shaped epitaxial region with shaping section

Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers

Semiconductor device and manufacturing method thereof

IC including standard cells and SRAM cells

Semiconductor device layout

STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE

Field-effect transistor devices with sidewall implant under bottom dielectric isolation

Multi-layer channel structures and methods of fabricating the same in field-effect transistors

Integrated circuit structure

Semiconductor device having contact plug

PMOSFET source drain

Asymmetric channel FinFETs with wrap around channel

LDD-free semiconductor structure and manufacturing method of the same

Semiconductor device

Electrostatic discharge protection devices and methods of forming electrostatic discharge protection devices

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device having stacked structure with two-dimensional atomic layer

Multi-gate device and method of fabrication thereof

Ultra-thin fin structure and method of fabricating the same

Method for forming source/drain contacts

Gate-all-around integrated circuit structures having fin stack isolation

Structure and method for integrated circuit

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

Isolation structure for stacked vertical transistors

Multi-gate metal-oxide-semiconductor field effect transistor

Method of manufacturing a semiconductor device and a semiconductor device

Semiconductor structure with improved source drain epitaxy

Semiconductor device structure with barrier layer

Semiconductor device

Integrated circuit with a fin and gate structure and method making the same

Bandgap reference circuit including vertically stacked active SOI devices

Spacer structures for semiconductor devices

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Semiconductor device structure having gate dielectric layer

FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES

Method of forming semiconductor device

Multi-gate device and method of fabrication thereof

Semiconductor device and method

Integrated circuit structure including asymmetric, recessed source and drain region and method for forming same

Methods for increasing germanium concentration of surfaces of a silicon germanium portion of a fin and resulting semiconductor devices

Semiconductor device with air-spacer

Method of manufacturing a semiconductor device and a semiconductor device

Wrap-around contact on FinFET

Stacked field effect transistor with wrap-around contacts

Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same

FETS and methods of forming FETS

Semiconductor device including fin structures and manufacturing method thereof

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Fin field-effect transistor device and method

Method for fabricating semiconductor structure

Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation

SEMICONDUCTOR DEVICE

Semiconductor structure and method for forming the same

Trench contact structures for advanced integrated circuit structure fabrication

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Integrated circuit structure with niobium-based silicide layer and methods to form same

Isolation structures of semiconductor devices

Semiconductor device and manufacturing method thereof

Method for FinFET LDD doping

Integrated assemblies having ferroelectric transistors with heterostructure active regions

Flexible merge scheme for source/drain epitaxy regions

Semiconductor structure with an epitaxial layer

Contact over active gate structures for advanced integrated circuit structure fabrication

Multi-layer thyristor random access memory with silicon-germanium bases

FinFET device and method of forming

Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same

Lateral heterojunction bipolar transistors with asymmetric junctions

Silicon and silicon germanium nanowire structures

Self-aligned interconnect with protection layer

Semiconductor devices

Gate line plug structures for advanced integrated circuit structure fabrication

Semiconductor device and manufacturing method thereof

Gate etch back with reduced loading effect

Source/drain feature to contact interfaces

Fins for metal oxide semiconductor device structures

Semiconductor epitaxy bordering isolation structure

FinFET device with high-K metal gate stack

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Insulated-gate bipolar transistor with enhanced frequency response, and related methods

Integrated circuit devices and methods of fabricating such devices

Interfacial layer between Fin and source/drain region

Field effect transistors with dual silicide contact structures

Semiconductor device having silicides and methods of manufacturing the same

Manufacturing method for semiconductor laminated film, and semiconductor laminated film

MOS devices having epitaxy regions with reduced facets

Nanowire transistor and manufacturing method thereof

Structure of a fin field effect transistor (FinFET)

Structure and formation method of semiconductor device structure with nanowires

Memory cell comprising a transistor that comprises a pair of insulator-material regions and an array of transistors

Diode

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Fin smoothing and integrated circuit structures resulting therefrom

GRAPHENE SEMICONDUCTOR JUNCTION DEVICE

Semiconductor devices having different numbers of stacked channels in different regions and methods of manufacturing the same

Semiconductor device having doped epitaxial region and its methods of fabrication

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Nanosheet transistor bottom isolation

Semiconductor device including epitaxial region having an extended portion

Semiconductor device and manufacturing method thereof

Semiconductor memory devices

Trench isolation for advanced integrated circuit structure fabrication

Semiconductor devices and methods of fabricating the same

Method for fabricating transistor with thinned channel

Bipolar junction transistor (BJT) comprising a multilayer base dielectric film

Conformal transfer doping method for fin-like field effect transistor

RF devices with nanotube particles for enhanced performance and methods of forming the same

Methods for forming a semiconductor structure and related semiconductor structures

Integrated circuit devices and methods of manufacturing the same

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Transistors with uniform source/drain epitaxy

Method for forming semiconductor device structure with cap layer

Doping profile for strained source/drain region

Semiconductor structure with blocking layer

Three-dimensional memory device having pocket structure in memory string and method for forming the same

Semiconductor device and method of fabricating the same

Source/drain structure having multi-facet surface

Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer

Semiconductor device and method of manufacture

GE based semiconductor device and a method for manufacturing the same

Devices including gate spacer with gap or void and methods of forming the same

Stress-inducing silicon liner in semiconductor devices

Semiconductor devices

Hybrid scheme for improved performance for P-type and N-type FinFETs

Semiconductor device and method for fabricating the same

Semiconductor method and device

Method of fabricating semiconductor device with metal pad extending into top metal layer

Replacement gate structures for advanced integrated circuit structure fabrication

Method of forming metal contact for semiconductor device

Virtual bulk in semiconductor on insulator technology

Stacked upper fin and lower fin transistor with separate gate

Semiconductor device having an upper epitaxial layer contacting two lower epitaxial layers

Semiconductor device and method for manufacturing the same

FinFET device and method of forming same

Supportive layer in source/drains of FinFET devices

Fin field effect transistor (FinFET) device and method for forming the same

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

Semiconductor device and manufacturing method thereof

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Self-aligned base and emitter for a bipolar junction transistor

Semiconductor devices including protruding insulation portions between active fins

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Photodiodes integrated into a BiCMOS process

Method to induce strain in finFET channels from an adjacent region

Semiconductor device with fin and related methods

Semiconductor process

IC including standard cells and SRAM cells

Semiconductor structure and fabricating method thereof

Semiconductor device and manufacturing method thereof

Metal-insensitive epitaxy formation

FinFET device with contact over dielectric gate

Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric

Semiconductor device with cap element

Semiconductor device

Method to induce strain in 3-D microfabricated structures

Semiconductor device and manufacturing method thereof

FinFET device having a channel defined in a diamond-like shape semiconductor structure

Gate voltage-tunable electron system integrated with superconducting resonator for quantum computing device

Lateral fin static induction transistor

Spacer structure with high plasma resistance for semiconductor devices

Semiconductor devices and method of manufacturing the same

Semiconductor device structure and method for preparing the same

Semiconductor device and method for fabricating the same

Methods of forming silicon germanium structures

Plugs for interconnect lines for advanced integrated circuit structure fabrication

Method of fabricating semiconductor device

Method of fabricating semiconductor device

Tunneling field effect transistor

Column IV transistors for PMOS integration

Contacts to n-type transistors with X-valley layer over L-valley channels

Method for forming semiconductor device having boron-doped germanium tin epitaxy structure

Semiconductor device and method for fabricating the same

MEMORY STRUCTURE

Semiconductor device

Transistors with uniform source/drain epitaxy

Strained structure of a semiconductor device

Semiconductor device

Middle of line structures

Semiconductor device and method of forming the same

Gradient doped region of recessed Fin forming a FinFET device

Semiconductor structure

Semiconductor device

Method for forming semiconductor device with helmet structure between two semiconductor fins

Semiconductor device structure with recessed spacer

Replacement gate structures for advanced integrated circuit structure fabrication

Semiconductor device including metal-2 dimensional material-semiconductor contact

HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS

Semiconductor devices and methods of manufacturing the same

Three-dimensional stackable multi-layer cross-point memory with bipolar junction transistor selectors

Source/drain features with an etch stop layer

Combination of tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors

Method of manufacturing a semiconductor device and semiconductor wafer

LDD-free semiconductor structure and manufacturing method of the same

Crystal orientation engineering to achieve consistent nanowire shapes

Method for fabricating a strained structure and structure formed

Structure and method for integrated circuit

Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof

Method for forming semiconductor device

Quantum dot devices

Systems and methods for a semiconductor structure having multiple semiconductor-device layers

One-time programmable device compatible with vertical transistor processing

Fin-based device having an isolation gate in physical contact with a source/drain

Transistor having strain-inducing anchors and a strain-enhancing suspended channel

Low-resistance contact plugs and method forming same

MOS devices having epitaxy regions with reduced facets

Method of manufacturing a semiconductor device with multilayered channel structure

Gate-all-around field effect transistors having end portions of nanosheet channel layers adjacent to source/drain regions being wider than the center portions

Nanosheet transistor having improved bottom isolation

Semiconductor device and method of forming doped channel thereof

Integrated circuits having source/drain structure and method of making

Source/drain junction formation

Gate stack structure and method for forming the same

Semiconductor device having interfacial layer and high κ dielectric layer

Formation of dislocations in source and drain regions of FinFET devices

Graphene structure and method of forming graphene structure

Electrical devices making use of counterdoped junctions

Source and drain stressors with recessed top surfaces

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Gate structure and method

Gate structure and method

Methods for forming recesses in source/drain regions and devices formed thereof

Semiconductor device with dielectric spacer liner on source/drain contact

Semiconductor device and method for fabricating the same

Static random access memory cell and manufacturing method thereof

Method of forming a transistor