208358 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed; Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi being a silicide layer, e.g. TiSi
Low Leakage FET
#2SEMICONDUCTOR DEVICE
#3MULTI-SILICIDE STACKED FIELD-EFFECT TRANSISTORS
#4Stacked Multi-Gate Device With Reduced Contact Resistance And Methods For Forming The Same
#5GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING TRENCH INTERNAL SPACER, AND METHOD FOR MANUFACTURING SAME
#6SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY
#7Methods Of Forming Contact Structure In Semiconductor Devices
#8SEMICONDUCTOR DEVICE
#9SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#10SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
#11Methods of Forming Semiconductor Devices Including Gate Barrier Layers
#12SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#13SELECTIVE SILICIDE FOR STACKED MULTI-GATE DEVICE
#14SEMICONDUCTOR DEVICES
#15WRAP-AROUND SILICIDE LAYER
#16MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES
#17SEMICONDUCTOR DEVICE WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOF
#18ETCHING PLATINUM-CONTAINING THIN FILM USING PROTECTIVE CAP LAYER
#19METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS
#20SEMICONDUCTOR DEVICE COMPRISING ALIGNMENT KEY
#21Semiconductor device
#22Semiconductor device with fin transistors and manufacturing method of such semiconductor device
#23SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#24PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT
#25Semiconductor device and manufacturing method thereof
#26Semiconductor device and manufacturing method thereof
#27Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#28CONNECTOR VIA STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME
#29Connector via structures for nanostructures and methods of forming the same
#30Enhanced channel strain to reduce contact resistance in NMOS FET devices
#31Ferroelectric capacitors
#32Semiconductor device and a method for fabricating the same
#33Low leakage FET
#34Semiconductor device with backside power rail and methods of fabrication thereof
#35Partial metal grain size control to improve CMP loading effect
#36Gate contact structures and cross-coupled contact structures for transistor devices
#37Semiconductor device and method
#38Semiconductor device with silicide gate fill structure
#39Methods of forming semiconductor devices including gate barrier layers
#40Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
#41Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#42Semiconductor device with a work function layer having an oxygen-blocking dopant layer
#43Selective capping processes and structures formed thereby
#44Threshold adjustment for quantum dot array devices with metal source and drain
#45Semiconductor device with backside power rail and methods of fabrication thereof
#46Structure and method to provide conductive field plate over gate structure
#47SOURCE OR DRAIN STRUCTURES WITH HIGH SURFACE GERMANIUM CONCENTRATION
#48Connector via structures for nanostructures and methods of forming the same
#49Semiconductor device with silicide gate fill structure
#50Metal gate structure and methods thereof
#51Semiconductor device and method
#52Semiconductor device with fin-type field effect transistor
#53Semiconductor device and manufacturing method thereof
#54Three-dimensional memory device employing thinned insulating layers and methods for forming the same
#55Semiconductor device including gate barrier layer
#56Etching platinum-containing thin film using protective cap layer
#57SEMICONDUCTOR DEVICE
#58METHODS FOR RELIABLY FORMING MICROELECTRONIC DEVICES WITH CONDUCTIVE CONTACTS TO SILICIDE REGIONS, AND RELATED SYSTEMS
#59Method of manufacturing a semiconductor device having a doped work-function layer
#60Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
#61Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#62Enhanced channel strain to reduce contact resistance in NMOS FET devices
#63Strained semiconductor device with improved NBTI and a method of making the same
#64Semiconductor device
#65Microelectronic devices with conductive contacts to silicide regions, and related devices
#66Semiconductor device
#67Semiconductor device having an upper epitaxial layer contacting two lower epitaxial layers
#68Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#69Transistor having airgap spacer around gate structure
#70Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
#71SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE
#72Semiconductor device and a method for fabricating the same
#73Low leakage FET
#74Semiconductor device with fin transistors and manufacturing method of such semiconductor device
#75Selective capping processes and structures formed thereby
#76Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material
#77Metal gate structure and methods thereof
#78Silicide structure of an integrated transistor device and method of providing same
#79Gate contact structures and cross-coupled contact structures for transistor devices
#80Transistor having blocks of source and drain silicides near the channel
#81Methods of forming integrated assemblies
#82Methods of fabricating integrated structures
#83Enhanced channel strain to reduce contact resistance in NMOS FET devices
#84Semiconductor device and a method for fabricating the same
#85Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#86Methods and apparatus for n-type metal oxide semiconductor (NMOS) metal gate materials using atomic layer deposition (ALD) processes with metal based precursors
#87Etching platinum-containing thin film using protective cap layer
#88Method for manufacturing insulated gate field effect transistor
#89METHODS, APPARATUS, AND SYSTEM TO CONTROL GATE HEIGHT AND CAP THICKNESS ACROSS MULTIPLE GATES
#90INTEGRATED CIRCUIT DEVICE WITH FARADAY SHIELD
#91Metal-insulator-metal (MIM) capacitor
#92Semiconductor devices
#93Semiconductor device
#94Gate structure with barrier layer and method for forming the same
#95Metal gate structure and methods thereof
#96Semiconductor device with fin transistors and manufacturing method of such semiconductor device
#97Semiconductor device with transistor portion having low injection region on the bottom of a substrate
#98Memory arrays and methods of fabricating integrated structure
#99Wide contact structure for small footprint radio frequency (RF) switch
#100Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#101Semiconductor device and a method for fabricating the same
#102Methods of filling horizontally-extending openings of integrated assemblies
#103Semiconductor device including MOS transistor having silicided source/drain region and method of fabricating the same
#104Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#105Transistors incorporating metal quantum dots into doped source and drain regions
#106Selective capping processes and structures formed thereby
#107Selective capping processes and structures formed thereby
#108Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#109Method for manufacturing multi-voltage devices using high-K-metal-gate (HKMG) technology
#110Temperature compensation circuits
#111Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
#112MOS-Gated Power Devices, Methods, and Integrated Circuits
#113Method for manufacturing gate stack structure
#114MOS-varactor design to improve tuning efficiency
#115Gate stacks
#116METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
#117Semiconductor device and manufacturing method thereof
#118Semiconductor device and method
#119Semiconductor device with airgap spacer for transistor and related method
#120Metal gate structure and methods thereof
#121Low thickness dependent work-function nMOS integration for metal gate
#122Enhanced channel strain to reduce contact resistance in NMOS FET devices
#123Low leakage FET
#124Substituted cyclopentadienyl cobalt complex and method for production thereof, and cobalt-containing thin film and method for production thereof
#125Semiconductor device having metal gate
#126Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#127Semiconductor device and manufacturing method thereof
#128Nanowire transistor having two spacers between gate structure and source/drain structure
#129Threshold adjustment for quantum dot array devices with metal source and drain
#130Semiconductor integrated circuit device and a method of manufacturing the same
#131Semiconductor device and method
#132SEMICONDUCTOR DEVICE
#133Method for manufacturing insulated gate field effect transistor
#134Field-effect transistors with a T-shaped gate electrode
#135Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
#136FinFET doping methods and structures thereof
#137Method for manufacturing a semiconductor device with a cobalt silicide film
#138Memory arrays and methods of fabricating integrated structures
#139Memory device and method of manufacturing the same
#140Etching platinum-containing thin film using protective cap layer
#141Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#142Semiconductor device and manufacturing method thereof
#143Semiconductor device and a method for fabricating the same
#144Semiconductor device and manufacturing method thereof
#145Temperature compensation circuits
#146Semiconductor device and a method for fabricating the same
#147Gap fill of metal stack in replacement gate process
#148Non-volatile memory
#149Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material
#150Control voltage searching method for non-volatile memory
#151Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#152Semiconductor device
#153Integrated circuit structure without gate contact and method of forming same
#154Memory device and method of manufacturing the same
#155Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof
#156Semiconductor device and manufacturing method thereof
#157MOS-varactor design to improve tuning efficiency
#158Semiconductor integrated circuit device and a method of manufacturing the same
#159Semiconductor memory device and method for manufacturing same
#160One time programmable (OTP) cell and an OTP memory array using the same
#161Process of forming metal-insulator-metal (MIM) capacitor
#162Transistor and fabrication method thereof
#163Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same
#164Semiconductor device and a method for fabricating the same
#165SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
#166Semiconductor device and manufacturing method thereof
#167Nanowire transistor and method for fabricating the same
#168METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI
#169Transistors incorporating metal quantum dots into doped source and drain regions
#170Semiconductor device including MOS transistor having silicided source/drain region and method of fabricating the same
#171Nonvolatile semiconductor memory device and method for manufacturing the same
#172Semiconductor device and a method for fabricating the same
#173Semiconductor device with FIN transistors and manufacturing method of such semiconductor device
#174Dielectric liner added after contact etch before silicide formation
#175Semiconductor device and a method for fabricating the same
#176Fully silicided linerless middle-of-line (MOL) contact
#177Gap fill of metal stack in replacement gate process
#178Enhanced channel strain to reduce contact resistance in NMOS FET devices
#179Semiconductor device with local interconnect structure and manufacturing method thereof
#180Self aligned gate shape preventing void formation
#181FinFET doping methods and structures thereof
#182Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material
#183Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#184Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#185Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#186Dummy gate used as interconnection and method of making the same
#187Method for producing one-time-programmable memory cells and corresponding integrated circuit
#188Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines
#189Semiconductor device and fabrication method thereof
#190Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching
#191Atomic layer deposition methods and structures thereof
#192Memory device containing cobalt silicide control gate electrodes and method of making thereof
#193Fully silicided linerless middle-of-line (MOL) contact
#194Highly scaled tunnel FET with tight pitch and method to fabricate same
#195Fully silicided linerless middle-of-line (MOL) contact
#196Semiconductor integrated circuit device and a method of manufacturing the same
#197Nanocrystalline diamond carbon film for 3D NAND hardmask application
#198Forming silicide regions and resulting MOS devices
#199Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#200Semiconductor device with a trench and method for manufacturing the same
#201Semiconductor device and manufacturing method of semiconductor device
#202Transistor with a low-k sidewall spacer and method of making same
#203Method for producing one-time-programmable memory cells and corresponding integrated circuit
#204Enhanced integration of DMOS and CMOS semiconductor devices
#205Method for forming metal semiconductor alloys in contact holes and trenches
#206Substrate cleaning method for removing oxide film
#207Insulated gate bipolar transistor structure having low substrate leakage
#208Gate stacks
#209Integrated circuit device and method of manufacturing the same
#210Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
#211Deep trench isolation for RF devices on SOI
#212Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#213Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
#214Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
#215High-reliability, low-resistance contacts for nanoscale transistors
#216METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
#217Methods of fabricating integrated structures
#218Low resistance replacement metal gate structure
#219Transistors incorporating metal quantum dots into doped source and drain regions
#220Semiconductor devices including silicide regions and methods of fabricating the same
#221Transistor and fabrication method thereof
#222Gate last semiconductor structure and method for forming the same
#223Threshold adjustment for quantum dot array devices with metal source and drain
#224METHOD FOR MAKING AN INTEGRATED CIRCUIT
#225Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching and the FinFETs thereof
#226Semiconductor devices and methods of fabricating the same
#227SEMICONDUCTOR DEVICE HAVING WORK FUNCTION CONTROL LAYER AND METHOD OF MANUFACTURING THE SAME
#228Salicide formation using a cap layer
#229Transistor device and fabrication method
#230Semiconductor device with partially unsilicided source/drain
#231SEMICONDUCTOR MEMORY
#232SEMICONDUCTOR MEMORY DEVICE
#233Display device
#234SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
#235Nanocrystalline diamond carbon film for 3D NAND hardmask application
#236Selective FuSi gate formation in gate first CMOS technologies
#237Backside source-drain contact for integrated circuit transistor devices and method of making same
#238Transistor having a vertical channel
#239HYBRID CONTACTS FOR COMMONLY FABRICATED SEMICONDUCTOR DEVICES USING SAME METAL
#240Transistor having a vertical channel
#241Integrated circuits with resistors
#242Method of fabricating semiconductor device having a resistor structure
#243Semiconductor devices and fabrication method thereof
#244Semiconductor device
#245Three dimensional semiconductor device having lateral channel
#246Three dimensional vertical NAND device with floating gates
#247Formation of metal resistor and e-fuse
#248Tunable breakdown voltage RF FET devices
#249Resistor memory bit-cell and circuitry and method of making the same
#250GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS
#251Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#252Semiconductor device, related manufacturing method, and related electronic device
#253Sacrificial oxide with uniform thickness
#254Memory arrays
#255Vertical NAND string multiple data line memory
#256Semiconductor devices and methods for manufacturing the same
#257SiC semiconductor device and method for manufacturing the same
#258Integrated circuit protected from short circuits caused by silicide
#259Semiconductor devices including a gate electrode and methods of manufacturing the same
#260Formation of metal resistor and e-fuse
#261Gate structures for transistor devices for CMOS applications and products
#262Semiconductor device and method for manufacturing the same
#263Semiconductor device and fabrication method thereof
#264Dielectric liner added after contact etch before silicide formation
#265Semiconductor memory device and method of fabricating the same
#266Electropositive metal containing layers for semiconductor applications
#267Semiconductor device and operating method thereof
#268Silicon carbide semiconductor device and method for manufacturing same
#269MOS-gated power devices, methods, and integrated circuits
#270Semiconductor device and method for forming the same
#271Conformal thin film deposition of electropositive metal alloy films
#272E-fuse design for high-K metal-gate technology
#273Body-contact metal-oxide-semiconductor field effect transistor device
#274Methods of manufacturing superjunction devices
#275Aqua regia and hydrogen peroxide HCL combination to remove Ni and NiPt residues
#276Method for making an integrated circuit
#277Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach
#278Semiconductor device and method for manufacturing the same
#279Method for manufacturing insulated gate field effect transistor
#280Semiconductor device having silicide on gate sidewalls in isolation regions
#281Semiconductor devices, transistors, and methods of manufacture thereof
#282FET dielectric reliability enhancement
#283SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#284Method for forming metal semiconductor alloys in contact holes and trenches
#285Method for forming metal semiconductor alloys in contact holes and trenches
#286Integrated circuits with resistors
#287Aqua regia and hydrogen peroxide HCI combination to remove Ni and NiPt residues
#288Method for providing a gate metal layer of a transistor device and associated transistor
#289Methods of forming metal silicide regions on a semiconductor device
#290CMOS Transistor with dual high-k gate dielectric
#291SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
#292Transistors, semiconductor devices, and electronic devices including transistor gates with conductive elements including cobalt silicide
#293Multiple data line memory and methods
#294Threshold adjustment for quantum dot array devices with metal source and drain
#295Transistors incorporating metal quantum dots into doped source and drain regions
#296Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material
#297Asymmetrical gate MOS device and method of making
#298SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
#299Methods for fabricating integrated circuits having improved metal gate structures
#300Metal silicide layer, NMOS transistor, and fabrication method