212383 ⎘
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Material of the semiconductor or solid state bodies; Semiconducting materials; Compound semiconductors; IV Silicon-germanium [SiGe]
STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTERPOSER CHIP
#2SEMICONDUCTOR DEVICE
#3PACKAGE WITH TILTED INTERFACE BETWEEN DEVICE DIE AND ENCAPSULATING MATERIAL
#4STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTERPOSER CHIP
#5MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME
#6SEMICONDUCTOR PACKAGES
#7SEMICONDUCTOR DEVICE
#8SEMICONDUCTOR DEVICE
#9Multi-chip package and method of providing die-to-die interconnects in same
#10Hybrid device assemblies and method of fabrication
#11INTEGRATED CIRCUIT AND RADIO-FREQUENCY MODULE
#12Forming Recesses in Molding Compound of Wafer to Reduce Stress
#13Semiconductor device
#14DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS
#15Semiconductor packages
#16Multi-chip package and method of providing die-to-die interconnects in same
#17Package with Tilted Interface Between Device Die and Encapsulating Material
#18Hybrid device assemblies and method of fabrication
#19Packages and methods of forming packages
#20System on integrated chips and methods of forming same
#21Semiconductor device
#22Package structures and methods of forming the same
#23Device and Method for UBM/RDL Routing
#24Multi-chip package and method of providing die-to-die interconnects in same
#25Sawing underfill in packaging processes
#26Through-Substrate Vias with Improved Connections
#27Direct substrate to solder bump connection for thermal management in flip chip amplifiers
#28Sawing underfill in packaging processes
#29Front-to-back bonding with through-substrate via (TSV)
#30Semiconductor package and method
#31Package structures and methods of forming the same
#32Semiconductor device
#33Package with tilted interface between device die and encapsulating material
#34Multi-chip package and method of providing die-to-die interconnects in same
#35Semiconductor device having metal bump and method of manufacturing the same
#36Electronic device, electronic module and methods for fabricating the same
#37Semiconductor chip
#38Forming recesses in molding compound of wafer to reduce stress
#39Methods and apparatus for scribe seal structures
#40System on integrated chips and methods of forming same
#41Packages and methods of forming packages
#42Dummy metal with zigzagged edges
#43Multi-chip package and method of providing die-to-die interconnects in same
#44Die bonder and methods of using the same
#45Die bonder and methods of using the same
#46Three dimensional integrated circuit (3DIC) with support structures
#47Superconducting bump bonds
#48Superconducting bump bonds
#49Device and method for UBM/RDL routing
#50Fabrication method of packaging structure
#51Module assembly
#52Through-substrate vias with improved connections
#53Spot-solderable leads for semiconductor device packages
#54Semiconductor chip and semiconductor package including the same
#55Semiconductor systems having dual leadframes
#56Semiconductor device having metal bump and method of manufacturing the same
#57Laser-releasable bonding materials for 3-D IC applications
#58Semiconductor device with bump structure and method of making semiconductor device
#59Semiconductor package and method
#60Large channel interconnects with through silicon Vias (TSVs) and method for constructing the same
#61Flip chip amplifier for wireless device
#62Dummy metal with zigzagged edges
#63Package with tilted interface between device die and encapsulating material
#64Packages and methods of forming packages
#65Package structures and methods of forming the same
#66Package structures and methods of forming the same
#67Integrated circuit packages and methods of forming same
#68Electrostatic discharge protection structure
#69Methods for producing packaged semiconductor devices
#70Semiconductor package with thermal fins
#71Flip-chip high speed components with underfill
#72Direct substrate to solder bump connection for thermal management in flip chip amplifiers
#73System on integrated chips and methods of forming same
#74Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
#75Chip on package structure and method
#76Superconducting bump bonds
#77Wafer level packaging method
#78Injection molded solder bumping
#79Multijunction solar cells on bulk GeSi substrate
#80Solution deposited magnetically guided chiplet displacement
#81Packaged semiconductor device having multi-level leadframes configured as modules
#82Advanced node cost reduction by ESD interposer
#83Package with tilted interface between device die and encapsulating material
#84Three dimensional integrated circuit (3DIC) with support structures
#85Packaging structure and fabrication method thereof
#86Method for applying a bonding layer
#87Multi-chip package and method of providing die-to-die interconnects in same
#88Front-to-back bonding with through-substrate via (TSV)
#89Package structures and methods of forming the same
#90Module assembly
#91Cryogenic electronic packages and assemblies
#92Electronic device, electronic module and methods for fabricating the same
#93Spot-solderable leads for semiconductor device packages
#94Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
#95Device and Method for UBM/RDL Routing
#96Method for wafer dicing
#97Through substrate vias with improved connections
#98Chip on package structure and method
#99Silicon package for embedded semiconductor chip and power converter
#100Redirecting solder material to visually inspectable package surface
#101Semiconductor devices, multi-die packages, and methods of manufacure thereof
#102Packages and methods of forming packages
#103Inter-chip alignment
#104Sawing underfill in packaging processes
#105Integrated circuit
#106Semiconductor package having a leadframe with multi-level assembly pads
#107Semiconductor systems having premolded dual leadframes
#108Solder bump placement for grounding in flip chip amplifiers
#109Solder bump placement for emitter-ballasting in flip chip amplifiers
#110Solder bump placement for thermal management in flip chip amplifiers
#111Configurable routing for packaging applications
#112Dummy metal with zigzagged edges
#113Wafer-level packaging using wire bond wires in place of a redistribution layer
#114Electronic apparatus and method for fabricating the same
#115Semiconductor devices and methods of manufacturing the same
#116High quality electrical contacts between integrated circuit chips
#117Forming recesses in molding compound of wafer to reduce stress
#118Via structures for thermal dissipation
#119Electronic apparatus and method for fabricating the same
#120Semiconductor arrangement, semiconductor system and method of forming a semiconductor arrangement
#121Semiconductor package
#122Flip chip module with enhanced properties
#123Semiconductor structure with sacrificial anode and method for forming
#124Electronic device including a metal substrate and a semiconductor module embedded in a laminate
#125Plastic-packaged semiconductor device having wires with polymerized insulating layer
#126Reliable microstrip routing for electronics components
#127Chip on package structure and method
#128Method of manufacturing semiconductor device and semiconductor device
#129Electronic apparatus and method for fabricating the same
#130Semiconductor device
#131Electronic component, semiconductor package, and electronic device using the same
#132Electronic part, electronic device, and manufacturing method
#133Front-to-back bonding with through-substrate via (TSV)
#134Method for applying a bonding layer
#135Wafer structure and method for wafer dicing
#136Through substrate vias with improved connections
#137Silicon package for embedded electronic system having stacked semiconductor chips
#138Interconnect structures for wafer level package and methods of forming same
#139Semiconductor device
#140Semiconductor devices, multi-die packages, and methods of manufacture thereof
#141Semiconductor device and method of forming the same
#142Packages and methods of forming packages
#143Electronic part, electronic device, and manufacturing method
#144Fan-out package structure and methods for forming the same
#145Integrated circuit package with radio frequency coupling structure
#146Integrated circuit packages and methods of forming same
#147Stacked dies with wire bonds and method
#148ULTRATHIN MICROELECTRONIC DIE PACKAGES AND METHODS OF FABRICATING THE SAME
#149Heat sink having a through-opening
#150Integrated electronic device including an interposer structure and a method for fabricating the same
#1513D integrated circuit package with through-mold first level interconnects
#152Methods for wafer bonding, and for nucleating bonding nanophases
#153Embedded die ball grid array package
#154Packages with stress-reducing structures and methods of forming same
#155Reliable microstrip routing for electronics components
#156Large channel interconnects with through silicon vias (TSVs) and method for constructing the same
#157Through via contacts with insulated substrate
#158Methods for forming semiconductor devices with stepped bond pads
#159Electronic apparatus and method for fabricating the same
#160Pattern generator having stacked chips
#161Semiconductor device and semiconductor device connection structure
#162Configurable routing for packaging applications
#163Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
#164Semiconductor device and method for manufacturing a semiconductor device
#165Integrated circuit combination of a target integrated circuit and a plurality of thin film photovoltaic cells connected thereto using a conductive path
#166Carrier-bonding methods and articles for semiconductor and interposer processing
#167Semiconductor device and method for manufacturing a semiconductor device
#168Structure and method for cooling three-dimensional integrated circuits
#169Packaging a semiconductor device having wires with polymerized insulator skin
#170Semiconductor device and method of manufacturing the same
#171Multichip device including a substrate
#172Electronic device and method for fabricating an electronic device
#173Front-to-back bonding with through-substrate via (TSV)
#174Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
#175Method for embedding controlled-cavity MEMS package in integration board
#176Ball height control in bonding process
#177Fan-out package structure and methods for forming the same
#178Semiconductor structure with sacrificial anode and passivation layer and method for forming
#179Semiconductor device, semiconductor package, and electronic system
#180Semiconductor package
#181Wafer scale technique for interconnecting vertically stacked dies
#182Chip arrangement and a method of manufacturing a chip arrangement
#183Guard ring design for maintaining signal integrity
#184Test structures for post-passivation interconnect
#185Laminate electronic device
#186Glass carrier with embedded semiconductor device and metal layers on the top surface
#187Semiconductor package and method for fabricating the same
#188Semiconductor packages having a guide wall and related systems and methods
#189Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages
#190Electric device package comprising a laminate and method of making an electric device package comprising a laminate
#191Method of fabricating wafer level package
#192Method for manufacturing semiconductor devices having a glass substrate
#193Wireless device, and information processing apparatus and storage device including the wireless device
#194Methods for embedding controlled-cavity MEMS package in integration board
#195Sawing underfill in packaging processes
#196Module including a discrete device mounted on a DCB substrate
#197Semiconductor Device and Fabrication Method
#198Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON
#199Package systems including passive electrical components
#200IC card and booking-account system using the IC card
#201Semiconductor device including a contact clip having protrusions and manufacturing thereof
#202Manufacturing electronic device having contact elements with a specified cross section
#203Semiconductor device with a layer including niobium, and/or tantalum overlying a contact pad or a metal layer
#204Multi-chip package and method of providing die-to-die interconnects in same
#205Method for manufacturing semiconductor devices having a glass substrate
#206Solder bump interconnect
#207Multichip Packages
#208IC card and booking-account system using the IC card
#209SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE
#210Chip-scale semiconductor die packaging method
#211Power/ground layout for chips
#212Manufacturing of a device including a semiconductor chip
#213Integrated circuit combination of a target integrated circuit and a plurality of photovoltaic cells connected thereto using the top conductive layer
#214Transition from a chip to a waveguide port
#215Semiconductor module and method for production thereof
#216Wireless communication device and semiconductor package device having a power amplifier therefor
#217Three-dimensional integrated circuit structure having improved power and thermal management
#218SEMICONDUCTOR DEVICE WITH INDUCTOR AND FLIP-CHIP
#219Multi-die stacking using bumps with different sizes
#220Method for manufacturing semiconductor devices having a glass substrate
#221Enhanced thermal management of 3-D stacked die packaging
#222Conductive pillar for semiconductor substrate and method of manufacture
#223Through-substrate vias with improved connections
#224WAFER LEVEL CHIP SCALE PACKAGE WITH ANNULAR REINFORCEMENT STRUCTURE
#225Ultra high speed signal transmission/reception
#226Bow-balanced 3D chip stacking
#227Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
#228METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE
#229MULTI-CHIP INTEGRATED CIRCUIT
#2303DIC Architecture with Die Inside Interposer
#231Solder bump interconnect
#232Bonded structure and manufacturing method for bonded structure
#2333D chip stack having encapsulated chip-in-chip
#234Chip assembly with chip-scale packaging
#235Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts
#236IC card and booking-account system using the IC card
#237Die stacking system and method
#238INTERPOSER, MODULE, AND ELECTRONICS DEVICE INCLUDING THE SAME
#2393-D semiconductor die structure with containing feature and method
#240Multi-chip package and method of providing die-to-die interconnects in same
#241High quality electrical contacts between integrated circuit chips
#242IC card and booking-account system using the IC card
#243Electronic device having contact elements with a specified cross section and manufacturing thereof
#2443-D semiconductor die structure with containing feature and method
#245FORMING EDGE METALLIC CONTACTS AND USING COULOMB FORCES TO IMPROVE OHMIC CONTACT
#246Forming large planar structures from substrates using edge Coulomb forces
#247Reconfigurable system that exchanges substrates using coulomb forces to optimize a parameter
#248Solder bump interconnect for improved mechanical and thermo-mechanical performance
#249Silicon carbide power devices including P-type epitaxial layers and direct ohmic contacts
#250Die stacking system and method
#251Wire Bonds Having Pressure-Absorbing Balls
#252Antenna device and radio communication device
#253Functional blocks for assembly
#254Power electronics equipments
#255Connection structure and method for fabricating the same
#256Substrate for device bonding and method for manufacturing same
#257Method for forming a double embossing structure
#258Semiconductor device and unit equipped with the same
#259Wire bonds having pressure-absorbing balls
#260Iridium oxide nanowires and method for forming same
#261Semiconductor assembly having substrate with electroplated contact pads
#262Sealing and protecting integrated circuit bonding pads
#263Sealing and protecting integrated circuit bonding pads
#264Bonding process with inhibited oxide formation
#265Bonding process with inhibited oxide formation
#266Electromagnetic wall in millimeter-wave cavity
#267Semiconductor structure and manufacturing method thereof
#268Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
#269Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity