212850 ⎘
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical effects; Effects and problems related to the device integration Bump effects
Sub-classes:Examination/Visualization/Collection System with Light Enhancement
#2PACKAGE SUBSTRATE AND FABRICATING METHOD THEREOF
#3SEMICONDUCTOR PACKAGE
#4INTERPOSER MODULE INCLUDING INTERCONNECTS WITH ALLOY BARRIER, PACKAGE STRUCTURE INCLUDING THE INTERPOSER MODULE AND METHODS OF MAKING THE SAME
#5SEMICONDUCTOR PACKAGE
#6METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE
#7SOLDER PREFORMS WITH EMBEDDED BEADS TO ACT AS STANDOFFS
#8ELECTRONIC CHIP WITH CONNECTION PILLARS
#9SEMICONDUCTOR DEVICE
#10SEMICONDUCTOR PACKAGE AND CHIP THEREOF
#11SEMICONDUCTOR DEVICE
#12METHODS AND APPARATUS TO REDUCE VARIATION IN HEIGHT OF BUMPS AFTER REFLOW
#13SEMICONDUCTOR PACKAGE
#14PACKAGING DEVICE INCLUDING BUMPS AND METHOD OF MANUFACTURING THE SAME
#15SEMICONDUCTOR DEVICE
#16SYSTEMS AND METHODS FOR REDUCING DIE SLIP DURING GROUP BONDING
#17CHIP STRUCTURE, SEMICONDUCTOR PACKAGE, AND FABRICATING METHOD THEREOF
#18BILAYER RDL STRUCTURE FOR BUMP COUNT REDUCTION
#19Bump structure having a side recess and semiconductor structure including the same
#20PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
#21SOLDER CREEP LIMITING RIGID SPACER FOR STACKED DIE C4 PACKAGING
#22PACKAGED MICROELECTRONIC DEVICES HAVING STACKED INTERCONNECT ELEMENTS AND METHODS FOR MANUFACTURING THE SAME
#23Bump structure having a side recess and semiconductor structure including the same
#24Bump layout for coplanarity improvement
#25Multilayer pillar for reduced stress interconnect and method of making same
#26Multilayer pillar for reduced stress interconnect and method of making same
#27Bump structure having a side recess and semiconductor structure including the same
#28Multilayer pillar for reduced stress interconnect and method of making same
#29Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
#30Monolithic decoupling capacitor between solder bumps
#31Leadless package with non-collapsible bump
#32Measurements of an integrated circuit chip and connected chip carrier to estimate height of interconnect
#33Bump structure having a side recess and semiconductor structure including the same
#34Mounting structure and method for manufacturing same
#35Multilayer pillar for reduced stress interconnect and method of making same
#36Method for fabricating package structure
#37Multilayer pillar for reduced stress interconnect and method of making same
#38Pillar design for conductive bump
#39Semiconductor device
#40CHIP AND MANUFACTURING METHOD THEREOF
#41Sloped bonding structure for semiconductor package
#42Electronic assembly that includes stacked electronic devices
#43Measurements of an integrated circuit chip and connected chip carrier to estimate height of interconnect
#44Package structure and fabrication method thereof
#45Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
#46STRESS SENSOR FOR A SEMICONDUCTOR DEVICE
#47Semiconductor device
#48Substrate structure and fabrication method thereof
#49INTEGRATED CIRCUITS INCLUDING COPPER PILLAR STRUCTURES AND METHODS FOR FABRICATING THE SAME
#50Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#51Ball grid array semiconductor package and method of manufacturing the same
#52Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
#53Mounting structure and method for manufacturing same
#54Semiconductor device for use in flip-chip bonding, which reduces lateral displacement
#55Package on package structure and method of manufacturing the same
#563D device packaging using through-substrate pillars
#57Semiconductor package
#58Bump electrode, board which has bump electrodes, and method for manufacturing the board
#59Pillar design for conductive bump
#60Integrated antennas in wafer level package
#61Bumping process and structure thereof
#62Bumping process and structure thereof
#63Pillar design for conductive bump
#64Multilayer pillar for reduced stress interconnect and method of making same
#65Interconnections for fine pitch semiconductor devices and manufacturing method thereof
#66Multilayer pillar for reduced stress interconnect and method of making same
#67Electronic component and electronic device
#68Integrated antennas in wafer level package
#69Ball grid array semiconductor package and method of manufacturing the same
#70Cu pillar bump with L-shaped non-metal sidewall protection structure
#71Bump, method for forming the bump, and method for mounting substrate having the bump thereon
#72Solder interconnect with non-wettable sidewall pillars and methods of manufacture
#73Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability
#74Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
#75Multilayer pillar for reduced stress interconnect and method of making same
#76Interconnections for fine pitch semiconductor devices and manufacturing method thereof
#77Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices