Patents-Review.com
ClassID:

221909 ⎘

H03K19/09425 - CPC Classification

Classification description:

Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits using specified components using semiconductor devices using field-effect transistors Multistate logic

Sub-classes:
Recent Application in this class:
#1
20260081585
2026-03-19

ROBUST SINGLE EVENT UPSET (SEU) TOLERANT HIGH-PERFORMANCE FLIP-FLOP

 #2
20250266813
2025-08-21

METHODS AND APPARATUS TO PERFORM CLOCK GATING

 #3
20250192784
2025-06-12

DUAL-EDGE-TRIGGERED FLIP-FLOPS INCLUDING SCAN, RESET, AND DATA RETENTION FEATURES

 #4
20240388281
2024-11-21

D FLIP-FLOP HAVING MULTIPLEXER FUNCTION

 #5
20240267047
2024-08-08

NON-BINARY COMPUTER USING ALTERNATING CURRENT

 #6
20240204782
2024-06-20

SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT

 #7
20240178841
2024-05-30

ADDRESSING FOR INTEGRATED CIRCUITS

 #8
20230170907
2023-06-01

Inverter including transistors having different threshold voltages and memory cell including the same

 #9
20220294447
2022-09-15

High-performance table-based state machine

 #10
20220094363
2022-03-24

Multibit multi-height cell to improve pin accessibility

 #11
20220085815
2022-03-17

High-performance table-based state machine

 #12
20220085017
2022-03-17

Transistor element, ternary inverter apparatus comprising same, and method for producing same

 #13
20210367601
2021-11-25

Multi-level drive data transmission circuit and method

 #14
20210305985
2021-09-30

Logic configuration techniques

 #15
20210175877
2021-06-10

Method for data storage and comparison, storage comparison circuit device, and semiconductor memory

 #16
20210099189
2021-04-01

Correction device

 #17
20200328743
2020-10-15

Signal-multiplexing device

 #18
20200210637
2020-07-02

Apparatus and method for ternary logic synthesis with modified Quine-McCluskey algorithm

 #19
20190045462
2019-02-07

Transmission power adjustment based on declared antenna gain

 #20
20180351508
2018-12-06

Oscillator

 #21
20180336856
2018-11-22

Scanning driver circuit and liquid crystal display panel

 #22
20170207783
2017-07-20

Three state latch

 #23
20170019278
2017-01-19

Circuits for and methods of generating a modulated signal in a transmitter

 #24
20150263729
2015-09-17

Carbon nanotube field-effect transistor encoder

 #25
20150236695
2015-08-20

Multi-threshold flash NCL logic circuitry with flash reset

 #26
20150109025
2015-04-23

AREA SAVING IN LATCH ARRAYS

 #27
20150070063
2015-03-12

Low power clock gated flip-flops

 #28
20140354330
2014-12-04

Three state latch

 #29
20130214814
2013-08-22

Self-ready flash null convention logic

 #30
20130214813
2013-08-22

Multi-threshold flash NCL circuitry

 #31
20110102024
2011-05-05

DATA OUTPUT CIRCUIT

 #32
20110068837
2011-03-24

Apparatus and method to tolerate floating input pin for input buffer

 #33
20110018517
2011-01-27

Multi-level signaling

 #34
20100026261
2010-02-04

Multi-level signaling

 #35
20090309630
2009-12-17

Ternary valve input circuit

 #36
20090129459
2009-05-21

Data receiver of semiconductor integrated circuit

 #37
20070092026
2007-04-26

Ternary pulse generation circuit

 #38
17305571
2022-05-03

Data sampling with loop-unrolled decision feedback equalization

 #39
17229277
2023-12-05

SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions

 #40
16707783
2020-09-15

Output buffer circuit with non-target ODT function

 #41
16379635
2020-01-07

Output buffer circuit with non-target ODT function

 #42
13890819
2014-06-10

Apparatus and method for three-level input detection