ClassID:

221910

H03K19/09429 - CPC Classification

Classification description:

Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits using specified components using semiconductor devices using field-effect transistors; Multistate logic one of the states being the high impedance or floating state

Recent Application in this class:
#1
20260039302
2026-02-05

CONTROLLING A GATE DRIVER WITH A TRISTATE CONTROL SIGNAL

#2
20250343548
2025-11-06

BLANKING PERIODS FOR SAFELY EXECUTING EXTERNAL TRISTATE REQUESTS

#3
20250202465
2025-06-19

Systems, Methods, and Devices of Tri-State Inverters

#4
20250038749
2025-01-30

CIRCUIT UNIT, LOGIC CIRCUIT, PROCESSOR, AND COMPUTING APPARATUS

#5
20240421820
2024-12-19

FAST DIGITAL ISOLATOR

#6
20240144980
2024-05-02

DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory

#7
20230058123
2023-02-23

Fast digital isolator

#8
20220255550
2022-08-11

Integrated transmitter slew rate calibration

#9
20220085813
2022-03-17

Digital driver using an analog operational amplifier

#10
20210183412
2021-06-17

Multi-chip devices

#11
20200312402
2020-10-01

Serializer

#12
20200212913
2020-07-02

Level converter and a method for converting level values in vehicle control devices

#13
20200021289
2020-01-16

Control of switches in a variable impedance element

#14
20190319612
2019-10-17

Ultra-Low Power Static State Flip Flop

#15
20190074823
2019-03-07

Multi-mode power train integrated circuit

#16
20190068195
2019-02-28

Clamp logic circuit

#17
20190028090
2019-01-24

Duty cycle detection

#18
20180331675
2018-11-15

Ultra-low power static state flip flop

#19
20180316349
2018-11-01

Control of switches in a variable impedance element

#20
20180152188
2018-05-31

System and method of driving a switch circuit

#21
20180138942
2018-05-17

Tristate and cross current free output buffer

#22
20180074788
2018-03-15

Ternary digit logic circuit

#23
20180048312
2018-02-15

Multi-format driver interface

#24
20170359070
2017-12-14

Semiconductor structure with back-gate switching

#25
20170331480
2017-11-16

Reconfigurable circuit

#26
20170264275
2017-09-14

Tri-state inverter, D latch and master-slave flip-flop comprising TFETs

#27
20170194943
2017-07-06

Ultra-low power static state flip flop

#28
20160301394
2016-10-13

Single wire interface

#29
20160269029
2016-09-15

LOGICAL SIGNAL DRIVER WITH DYNAMIC OUTPUT IMPEDANCE AND METHOD THEREOF

#30
20160142057
2016-05-19

Compact logic evaluation gates using null convention

#31
20160036446
2016-02-04

Cross point switch

#32
20160036428
2016-02-04

Fine-grained power gating in FPGA interconnects

#33
20150303925
2015-10-22

Output buffer, gate electrode driving circuit and method for controlling the same

#34
20150091609
2015-04-02

Integrated circuit with signal assist circuitry and method of operating the circuit

#35
20140347095
2014-11-27

Bidirectional buffer and control method thereof

#36
20140340118
2014-11-20

Tristate gate

#37
20140285237
2014-09-25

Tri-state driver circuits having automatic high-impedance enabling

#38
20140285236
2014-09-25

Flip-flop circuit with resistive poly routing

#39
20140219036
2014-08-07

Equalizer and semiconductor memory device including the same

#40
20130285725
2013-10-31

Duty cycle distortion correction circuitry

#41
20130120044
2013-05-16

Duty cycle distortion correction circuitry

#42
20120280842
2012-11-08

System and method for supporting different types of oscillator circuits

#43
20120229164
2012-09-13

Output circuit and output control system

#44
20120218008
2012-08-30

Tri-state driver circuits having automatic high-impedance enabling

#45
20100177578
2010-07-15

Tri-state driver circuits having automatic high-impedance enabling

#46
20100156504
2010-06-24

Cross point switch

#47
20090206937
2009-08-20

Inverting cell

#48
20090184737
2009-07-23

Semiconductor device having input circuit with auxiliary current sink

#49
20090115504
2009-05-07

Circuit design methodology to reduce leakage power

#50
20090096483
2009-04-16

Asynchronous clock gate with glitch protection

#51
20090066372
2009-03-12

High speed CMOS output buffer for nonvolatile memory devices

#52
20090033363
2009-02-05

Multi-function input terminal

#53
20080303548
2008-12-11

SEMICONDUCTOR DEVICE

#54
20080224733
2008-09-18

Electronic circuit for maintaining and controlling data bus state

#55
20080143410
2008-06-19

Clock Input/Output Device

#56
20080100340
2008-05-01

Low voltage complementary metal oxide semiconductor process tri-state buffer

#57
20080079475
2008-04-03

Buffer Circuit and control method thereof

#58
20080054970
2008-03-06

Voltage conveyor for changing voltage levels in a controlled manner

#59
20080007295
2008-01-10

Tri-stated driver for bandwidth-limited load

#60
20070176633
2007-08-02

Output circuit

#61
20070152711
2007-07-05

LEVEL SHIFTER OUTPUT BUFFER CIRCUIT USABLE AS AN ISOLATION CELL

#62
20070085577
2007-04-19

High frequency transmission gate buffer

#63
20060244486
2006-11-02

Anticipatory programmable interface pre-driver

#64
20060186921
2006-08-24

Dual-voltage three-state buffer circuit with simplified tri-state level shifter

#65
20050270064
2005-12-08

Semiconductor device

#66
20050206585
2005-09-22

Display devices and integrated circuits

#67
20050122156
2005-06-09

Level-shifting circuitry having “high” output impedance during disable mode

#68
20050062509
2005-03-24

Buffer/voltage-mirror arrangements for sensitive node voltage connections

#69
16368728
2020-02-25

Serializer

#70
16213010
2019-07-30

Digital circuit based on a modified tristate circuit

#71
15677989
2018-11-06

Multi-mode power train integrated circuit

#72
15663209
2018-08-28

Augmented intermediate voltage generator based core to pad level shifter

#73
15182068
2017-09-12

Semiconductor structure with back-gate switching

#74
14642768
2016-06-14

Multiplexer circuit