DIVIDER CIRCUIT

CAPACITANCE SENSOR ARRAY CHIP WITH PROGRAMMABLE FUSION PIXELS, SAMPLING DEVICE THEREOF AND CONTROLLING SYSTEM THEREOF

PHASE FREQUENCY DETECTOR AND ITS METHOD OF OPERATION

DUAL-EDGE-TRIGGERED FLIP-FLOPS INCLUDING SCAN, RESET, AND DATA RETENTION FEATURES

SENSE AMPLIFIER BASED FLIP-FLOP

CIRCUITS AND METHODS TO HARVEST ENERGY FROM TRANSIENT ON-CHIP DATA

CIRCUITS AND METHODS TO USE ENERGY HARVESTED FROM TRANSIENT ON-CHIP DATA

PHYSICALLY UNCLONABLE FUNCTION (PUF) GENERATION

CLOCK MULTIPLEXING CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING THE CLOCK MULTIPLEXING CIRCUIT

LOGIC OPERATION CIRCUIT, DIFFERENTIAL AMPLIFIER CIRCUIT, AND ELECTRONIC DEVICE

Circuits and methods for generating data outputs utilized shared clock-activated transistors

Reduced-power dynamic data circuits with wide-band energy recovery

CIRCUITS & METHODS TO HARVEST ENERGY FROM TRANSIENT DATA

Adaptive keeper for supply-robust circuits

Low power single phase logic gate latch for clock-gating

Hardness amplification of physical unclonable functions (PUFS)

Circuits and methods to use energy harvested from transient on-chip data

Physically unclonable function (PUF) generation

Semiconductor device

CAN BUS TRANSMITTER

Circuits and methods to harvest energy from transient on-chip data

Circuit performing logical operation and flip-flop including the circuit

Clock distribution circuit and semiconductor apparatus including the same

Synchronization circuit, a serializer using the synchronization circuit, and a data output circuit using the synchronization circuit and the serializer

CLOCKED LATCH CIRCUIT AND A CLOCK GENERATING CIRCUIT USING THE SAME

Physically unclonable function (PUF) generation

Reduced-power dynamic data circuits with wide-band energy recovery

Bootstrapped switch

Leakage current reduction in electronic devices

Leakage current reduction in electronic devices

Apparatus for generating secret information on basis of ring oscillator architecture and method of same

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

Reduced-power dynamic data circuits with wide-band energy recovery

Dynamic decode circuit with active glitch control

Dynamic decode circuit with delayed precharge

Dynamic decode circuit with active glitch control method

Dynamic decode circuit with active glitch control method

Multi-level adiabatic charging methods, devices and systems

Dynamic decode circuit with active glitch control

Dynamic decode circuit with active glitch control

Adaptive pulse generation circuits for clocking pulse latches with minimum hold time

Level shifter and a method for shifting voltage level

Low power wideband non-coherent binary phase shift keying demodulator to align the phase of sideband differential output comparators for reducing jitter, using first order sideband filters with phase 180 degree alignment

Method of obfuscating digital logic circuits using threshold voltage

Muller C-element as majority gate for self-correcting triple modular redundant logic with low-overhead modes

Adaptive dynamic keeper circuit

Integrated clock gater (ICG) using clock cascode complimentary switch logic

Threshold logic element with stabilizing feedback

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Integrated clock gater (ICG) using clock cascode complimentary switch logic

Leakage reduction in output driver circuits

Integrated circuit with signal assist circuitry and method of operating the circuit

Circuit for reducing negative bias temperature instability

Ternary T arithmetic circuit

In situ pulse-based delay variation monitor predicting timing error caused by process and environmental variation

Semiconductor device

Time division multiplexed limited switch dynamic logic

Semiconductor integrated circuit

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Semiconductor integrated circuit

Clock-delayed domino logic circuit and devices including the same

Footer-less NP domino logic circuit and related apparatus

Keeper Circuit And Electronic Device Having The Same

Clock-delayed domino logic circuit

Multi-threshold sleep convention logic without nsleep

Data output circuit and operating method with reduced current overlap for semiconductor device

Selector circuit and processor system

Apparatus and method for converting static memory address to memory address pulse

Split decode latch with shared feedback

One-of-n N-nary logic implementation of a storage cell

Semiconductor integrated circuit

Semiconductor device

Semiconductor device

Apparatus for clocked power logic against power analysis attack

Digital logic circuit with dynamic logic gate

Selector circuit and processor system

Clocked inverter, NAND, NOR and shift register

Circuit for reducing negative bias temperature instability

Flip-flop circuit and leakage current suppression circuit utilized in a flip-flop circuit

Voltage level shifter with dynamic circuit structure having discharge delay tracking

Voltage level shifter with dynamic circuit structure having discharge delay tracking

Semiconductor device

Circuit device, electronic apparatus, and power supply method

Semiconductor integrated circuit

Keeper circuit

Dynamic circuit with slow mux input

Dynamic domino circuit and integrated circuit including the same

Semiconductor device

Logic gate with a reduced number of switches, especially for applications in integrated circuits

Domino logic block having data holding function and domino logic including the domino logic block

Complementary energy path adiabatic logic

Dual gate transistor keeper dynamic logic

Fast turn on active DCAP cell

Domino logic circuit and pipelined domino logic circuit

Clocked inverter, NAND, NOR and shift register

High performance clocked latches and devices therefrom

HIGH PERFORMANCE LATCHES

FULLY INTERRUPTIBLE DOMINO LATCH

High performance pulsed buffer

Structure for a Limited Switch Dynamic Logic Cell Based Register

Limited switch dynamic logic cell based register

Systems and methods for dynamic logic keeper optimization

Local clock buffer (LCB) with asymmetric inductive peaking

Dynamic dual output latch

Local clock buffer (LCB) with asymmetric inductive peaking

Design structure for a current control mechanism for power networks and dynamic logic keeper circuits

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

Clocked inverter, NAND, NOR and shift register

Hybrid Keeper Circuit for Dynamic Logic

Dynamic floating input D flip-flop

Current Mirror and Parallel Logic Evaluation

Bistable circuit with auto-time-adjusted switching, and flip-flop using such a bistable circuit

Domino Circuit with Master and Slave (DUAL) Pull Down Paths

Accelerated P-channel dynamic register

Accelerated N-channel dynamic register

P-domino register with accelerated non-charge path

N-domino register with accelerated non-discharge path

Circuit and method for configuring a circuit

Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits

Circuit and method for latch bypass

Low swing current mode logic family

AND type match circuit structure for content-addressable memories

Dynamic logic with adaptive keeper

Dual redundant dynamic logic

CMOS circuit arrangement

Semiconductor integrated circuit

Flip-flop with improved operating speed

High speed, low power CMOS logic gate

Dual-gate dynamic logic circuit with pre-charge keeper

Circuit and method for calculating a logical combination of two input operands

Scan friendly domino exit and domino entry sequential circuits

Circuit and method for calculating a logic combination of two encrypted input operands

Maskable dynamic logic

Scannable dynamic circuit latch

Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock

Independent gate control logic circuitry

Dual gate transistor keeper dynamic logic

Keeper circuits having dynamic leakage compensation

Controlled load limited switch dynamic logic circuitry

Logic circuits utilizing gated diode sensing

Fast pulse powered NOR decode apparatus for semiconductor devices

Clocked preconditioning of intermediate nodes

Inverting dynamic register with data-dependent hold time reduction mechanism

Methods of forming semiconductor constructions and integrated circuits

Unfooted domino logic circuit and method

Body biasing for dynamic circuit

Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers

Systems and methods for reducing timing variations by adjusting buffer drivability

Dynamic logic circuit incorporating reduced leakage state-retaining devices

Leakage-tolerant dynamic wide-NOR circuit structure

Logic circuitry

Circuit and circuit design method

Leakage sensing and keeper circuit for proper operation of a dynamic circuit

Dynamic latching logic structure with static interfaces for implementing improved data setup time

Event-driven logic circuit

P-domino output latch

P-domino register

Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation

N-domino output latch

Dynamic circuit

Dynamic latch having integral logic function and method therefor

Semiconductor device

Semiconductor constructions and integrated circuits

Method, apparatus and system of domino multiplexing

Pseudo-CMOS dynamic logic with delayed clocks

P-domino output latch with accelerated evaluate path

MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop

Monotonic leakage-tolerant logic circuits

Generalized pre-charge clock circuit for pulsed domino gates

Single stage level restore circuit with hold functionality

Control circuits and methods including delay times for multi-threshold CMOS devices

Circuit for controlling the time duration of a signal

Power converter circuitry and method

Midcycle latch for power saving and switching reduction

Non-inverting domino register

Circuit and associated methodology

Feedforward limited switch dynamic logic circuit

Low switching power limited switch dynamic logic

Multistage dynamic domino circuit with internally generated delay reset clock

Data input/output buffer and semiconductor memory device using the same

Retention device for a dynamic logic stage

Resonant logic and the implementation of low power digital integrated circuits

Dynamic logic return-to-zero latching mechanism

Duo-mode keeper circuit

Limited switch dynamic logic circuit with keeper

Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates

Methods and arrangements for enhancing domino logic

Pseudo CMOS dynamic logic with delayed clocks

Dynamic circuits having improved noise tolerance and method for designing same

Integrated logic and latch design with clock gating at static input signals

High spurious-free dynamic-range line driver

Master-slave clock generation circuit

Dynamic decode circuit with active glitch control

Integrated circuit power reduction through charge

Dynamic flip-flop and multiplexer for sub-rate clock data serializer

Device for maintaining synchronization of plurality of field programmable gate arrays (FPGAs)