ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER

PROCESSING CHIP, DESIGN METHOD, AND ELECTRONIC DEVICE

LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE

RESET INDEPENDENT GLITCH FILTER

DYNAMIC LATCH, SEMICONDUCTOR CHIP, COMPUTING POWER BOARD AND COMPUTING DEVICE

ISOLATED DRIVER DEVICE, CORRESPONDING ELECTRONIC SYSTEM AND METHOD OF TRANSMITTING A DATA SIGNAL ACROSS A GALVANIC ISOLATION BARRIER

Logic circuit and semiconductor device

SEMICONDUCTOR DEVICES HAVING PARALLEL-TO-SERIAL CONVERTERS THEREIN

Programmable logic array with reliable timing

EFFECTIVE SYNCHRONOUS GATES FOR RAPID SINGLE FLUX QUANTUM LOGIC

Logic circuit and semiconductor device

Multi-bit scan chain with error-bit generator

Clock enabler circuit

Transmitter circuit, corresponding isolated driver device, electronic system and method of encoding a pulse-width modulated signal into a differential pulsed signal

Property-Driven Automatic Generation of Reduced Component Hardware

High-performance table-based state machine

Clock-gating synchronization circuit and method of clock-gating synchronization

High-performance table-based state machine

Information processing apparatus and non-transitory computer readable medium

Storage circuit with hardware read access

Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks

LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE

Deglitching circuit and method in a class-D amplifier

Memory interface circuit including output impedance monitor and method of calibrating output impedance thereof

Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges

Frequency divider circuit, communication circuit, and integrated circuit

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Circuit including flip-flop and control element

Deglitching circuit and method in class-D amplifier

Logic circuit and semiconductor device

Synchronous device with slack guard circuit

SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND TRANSPARENCY ON BOTH INPUT DATA EDGES

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

System, apparatus and method for providing a local clock signal for a memory array

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Distributed programmable delay lines in a clock tree

Low-power multi-phase clock distribution on silicon

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Wiring with external terminal

Wiring with external terminal

Logic circuit and semiconductor device

System, apparatus and method for providing a local clock signal for a memory array

Hold-time compensation using free metal segments

Shift register and a driving method thereof, a gate driving circuit and a display device

Control circuit of power gating and semiconductor device

Semiconductor device and semiconductor system

Register circuit

3D semiconductor structure and device

Hum generation using representative circuitry

D flip-flop and signal driving method

Logic circuit and semiconductor device

METASTABILITY GLITCH DETECTION

Semiconductor integrated circuit capable of precisely adjusting delay amount of strobe signal

Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit

Driver circuit comprising semiconductor device

Semiconductor device and structure

Clock-tree transformation in high-speed ASIC implementation

Synchronized logic circuit

Pulse output circuit, shift register, and display device

Multi-threshold flash NCL logic circuitry with flash reset

Time division multiplexed limited switch dynamic logic

Clock-tree transformation in high-speed ASIC implementation

Metastability glitch detection

Time division multiplexed limited switch dynamic logic

Semiconductor device and structure

Resonant inductor coupling clock distribution

Clock synchronization circuit and semiconductor device

Semiconductor device with a small off current and oxide semiconductor layer having a function of a channel formation layer

Distributed current clock for nano-magnetic element array

Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption

Margin improvement for configurable local clock buffer

Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit

Semiconductor integrated circuit capable of precisely adjusting delay amount of strobe signal

Pipelining of clock guided logic using latches

System, method, and computer program product for automatic two-phase clocking

Minimizing power consumption in asynchronous dataflow architectures

Crosstalk mitigation in on-chip interfaces

Resonant inductor coupling clock distribution

Systems and methods for reduced coupling between digital signal lines

Coarse gating of clock tree elements

Clock network architecture

Low swing dynamic circuit

Time division multiplexed limited switch dynamic logic

Hum generation circuitry

Clock synchronization circuit and semiconductor device

Time division multiplexed limited switch dynamic logic

Time division multiplexed limited switch dynamic logic

Semiconductor integrated circuit

Homogeneous dual-rail logic for DPA attack resistive secure circuit design

Clock-delayed domino logic circuit and devices including the same

Preventing A-B-A race in a latch-based device

Pseudo-static domino logic circuit and apparatuses including same

Clock-delayed domino logic circuit

Single clock distribution network for multi-phase clock integrated circuits

METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES

Clock-tree transformation in high-speed ASIC implementation

Logic circuit

Logic circuit and semiconductor device

Pulse signal output circuit and shift register

Selector circuit and processor system

Integrated circuit including pulse control logic having shared gating control

Digital test system and method for value based data

Pulse signal output circuit and shift register

Preventing A-B-A race in a latch-based device

Logic circuit and semiconductor device

Serializing transmitter

Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption

Shift register with low power consumption

Circuit for detecting and preventing setup fails and the method thereof

Clock-tree transformation in high-speed ASIC implementation

Shift register with low power consumption

Translation Lookaside Buffer Structure Including a Data Array Having an Integrated Multiplexer

Translation lookaside buffer structure including an output comparator

Translation Lookaside Buffer Structure Including a Data Array Storing an Address Selection Signal

Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit

Integrated circuit including pulse control logic having shared gating control

Homogeneous dual-rail logic for DPA attack resistive secure circuit design

Selector circuit and processor system

Clock management unit and method of managing a clock signal

Shift register with low power consumption

Method and apparatus to serialize parallel data input values

Logic circuit

Pulse signal output circuit and shift register

Pulse signal output circuit and shift register

Clock generator circuits for generating clock signals

Semiconductor device and method for operating the same

Method and apparatus for gating a clock signal

Shift register with low power consumption

Logic circuit and semiconductor device

Logic circuit and semiconductor device

Multi-level domino, bundled data, and mixed templates

Semiconductor integrated circuit

Clock guided logic with reduced switching

Logic circuit

INVERTER CIRCUIT

Adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique

Complementary energy path adiabatic logic

Dual rail domino circuit and logic circuit

Compound logic flip-flop having a plurality of input stages

High Speed "Pseudo" Current Mode Logic (CML) Integrated Circuit Memory Latch

DYNAMIC SEMICONDUCTOR DEVICE

Clock guided logic with reduced switching

Virtual power rail modulation within an integrated circuit

Single threshold and single conductivity type logic

Shift register circuit and image display apparatus containing the same

Pulse output circuit, shift register, and display device

Scannable dynamic logic latch circuit

DUAL-EDGE-TRIGGERED, CLOCK-GATED LOGIC CIRCUIT AND METHOD

Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)

Integrated circuit

Pulse output circuit, shift register, and display device

Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers

Latch-based serial port output buffer

Pseudo-CMOS dynamic logic with delayed clocks

Pseudo CMOS dynamic logic with delayed clocks

Data sampling with loop-unrolled decision feedback equalization

Buffer output circuit, driving method thereof and memory apparatus

Selectively providing clock signals using a programmable control circuit

2D compression-based low power ATPG

Glitch-free clock switching circuit using Muller C-elements

Power gating and clock gating in wiring levels

Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same

Dynamic flip-flop and multiplexer for sub-rate clock data serializer

Modified standard cells to address fast paths

Method and apparatus for clocking

Semiconductor device and structure