221965 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form; Structural details for adapting physical parameters for input/output [I/O] voltages
CIRCUITS AND METHODS FOR WAKE-UP RECEIVERS
#2MEMORY CONTROLLER
#3UNIVERSAL LOGIC MEMORY BLOCK USING UNIVERSAL LOGIC MEMORY CELLS
#4Voltage Domain GPIO Control
#5Interface system and memory system including the same
#6Circuits and methods for wake-up receivers
#7Apparatus for controlling in-rush current and an operation method thereof
#8Method and Apparatus for Providing Multiple Power Domains in A Programmable Semiconductor Device
#9CONTROL CIRCUIT, METHOD AND SYSTEM
#10Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains
#11Multiplexer
#12Power chip with a multi-function pin
#13Low frequency power supply spur reduction in clock signals
#14Adaptive biasing circuit for serial communication interfaces
#15Interface circuit and interface device
#16Method and apparatus for providing multiple power domains to a programmable semiconductor device
#17Memory system
#18COMPUTER SYSTEM AND INTERFACE CIRCUIT THEREFOR
#19CIRCUITS AND METHODS FOR WAKE-UP RECEIVERS
#20Transmitter and receiver for low power input/output and memory system including the same
#21Method and apparatus for providing multiple power domains a programmable semiconductor device
#22Circuit systems and methods for reducing power supply voltage droop
#23Output driving circuit
#24Voltage driving circuit
#25Failsafe device
#26Mechanical input/output selector
#27Output driving circuit
#28Generating analog output from a field programmable gate array by combining scaled digital outputs
#29Output driving circuit
#30Circuits for and methods of generating a modulated signal in a transmitter
#31Programmable High-Speed I/O Interface
#32Programmable High-Speed I/O Interface
#33Methods and apparatuses for sub-threhold clock tree design for optimal power
#34Configurable output driver ASIC
#35Input/output circuits and methods of implementing an input/output circuit
#36Monolithic integrated circuit die having modular die regions stitched together
#37Programmable high-speed I/O interface
#38Programmable high-speed I/O interface
#39Sub-threshold FPGA and related circuits and methods thereof
#40Programmable high-speed interface
#41Apparatus and methods for adjusting performance of programmable logic devices
#42Power control of an integrated circuit including an array of interconnected configurable logic elements
#43PROGRAMMABLE HIGH-SPEED INTERFACE
#44Programmable high-speed interface
#45Logic circuit system and method of changing operating voltage of a programmable logic circuit
#46Logic circuit system and method of changing operating voltage of a programmable logic circuit
#47Logic circuit system and method of changing operating voltage of a programmable logic circuit
#48Apparatus and methods for adjusting performance of programmable logic devices
#49Configurable I/Os for multi-chip modules
#50Programmable high speed interface
#51Logic circuit system and method of changing operating voltage of a programmable logic circuit
#52Programmable high speed I/O interface
#53Voltage domain GPIO control
#54Asynchronous circuit stacking for simplified power management
#55Low-current circuits for supply voltage level detection
#56Generating analog output from a field programmable gate array by combining scaled digital outputs
#57Extended voltage range coldspare tolerant off chip driver