TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

Training and operations with a double buffered memory topology

Training and operations with a double buffered memory topology

Circuits and methods for detecting decreases in a supply voltage in an integrated circuit

Methods for programing DDR compatible open architecture resistive change element arrays

Training and operations with a double buffered memory topology

Resistive change element arrays using a reference line

Logic circuits with augmented arithmetic densities

3D package having edge-aligned die stack with direct inter-die wire connections

Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison

Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features

Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features

Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Resistive change element arrays with in situ initialization

DDR compatible open array architectures for resistive change element arrays

Semiconductor device, electronic component, and electronic device

Correlated electron switch device

Methods for programming and accessing DDR compatible resistive change element arrays

Training and operations with a double buffered memory topology

Robust, low power, reconfigurable threshold logic array

Programmable logic circuit and nonvolatile FPGA

Security shield assembly

Reprogrammable logic device resistant to radiations

Input/output circuits and methods of implementing an input/output circuit

Programmable LSI with multiple transistors in a memory element

PLD architecture for flexible placement of IP function blocks

Programmable logic device structure using third dimensional memory

Programmable LSI

Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore

Re-programmable antifuse FPGA utilizing resistive CeRAM elements

Field programmable gate arrays using resistivity-sensitive memories

FIELD PROGRAMMABLE GATE ARRAY

PLD architecture for flexible placement of IP function blocks

Programmable LSI

3D semiconductor device

Method to form a 3D semiconductor device

3D semiconductor device

3D semiconductor device

Programmable logic device structure using third dimensional memory

Non-volatile logic circuit

Software programmable logic using spin transfer torque magnetoresistive devices

Field programmable gate arrays using resistivity-sensitive memories

Gate array

Architecture and interconnect scheme for programmable logic circuits

Semiconductor device and structure

METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE

Semiconductor device

Inverting flip-flop for use in field programmable gate arrays

Configuration random access memory

Configurable circuit and configuration method

Apparatus and method for forming a mixed signal circuit with fully customizable analog cells and programmable interconnect

Method for fabrication of a semiconductor element and structure thereof

Method for fabrication of a semiconductor element and structure thereof

Semiconductor device configuration method

Array and control method for flash based FPGA cell

Software programmable logic using spin transfer torque magnetoresistive devices

Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR

Field programmable gate arrays using resistivity sensitive memories

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Programmable logic device structure using third dimensional memory

Method and apparatus for safe power up of programmable interconnect

Memory based computation systems and methods of using the same

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Programmable logic circuit

ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Semiconductor integrated circuit device

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Integrated three-dimensional semiconductor system comprising nonvolatile nanotube field effect transistors

APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS

Programmable switch circuit and method, method of manufacture, and devices and systems including the same

IC having programmable digital logic cells

Passgate structures for use in low-voltage applications

PROGRAMMABLE ARRAY LOGIC CIRCUIT EMPLOYING NON-VOLATILE FERROMAGNETIC MEMORY CELLS

PLD architecture for flexible placement of IP function blocks

Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor

Logic element, and integrated circuit or field programmable gate array

Programmable logic device structure using third dimensional memory

Field programmable gate arrays using resistivity sensitive memories

Reconfigurable logic structures

DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES

Programmable interconnect structures

Switching circuits and methods for programmable logic devices

Efficient delay elements

Semiconductor device

Programmable computing array

APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY

Architecture and interconnect scheme for programmable logic circuits

Integrated circuit switching device, structure and method of manufacture

Block symmetrization in a field programmable gate array

Apparatus, method and computer program product providing radial addressing of nanowires

Semiconductor integrated circuit device

FPGA architecture at conventional and submicron scales

Software programmable logic using spin transfer torque magnetoresistive random access memory

Method and device for programming anti-fuses

SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABLE GATE ARRAY

PROGRAMMABLE ANTI-FUSE BASED ON, E.G., ZNCDS MEMORY DEVICES FOR FPGA AND OTHER APPLICATIONS

Configuration random access memory

Programming matrix

Programmable logic cell, configurable cell, configurable cell arrangement, configurable logic array, mask programmable basic cell, mask programmable gate array and method

Cells of a customizable logic array device having independently accessible circuit elements

Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA

Non-volatile memory cells in a field programmable gate array

Configurable embedded multi-port memory

Reconfigurable programmable logic device with P-channel non-volatile memory cells

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

System for configuring an integrated circuit and method thereof

Programmable array logic circuit employing non-volatile ferromagnetic memory cells

Antifuse programming circuit with snapback select transistor

Memory based computation systems and methods of using the same

Programmable semiconductor device

Block symmetrization in a field programmable gate array

Synchronous first-in/first-out block memory for a field programmable gate array

FPGA architecture at conventional and submicron scales

Reconfigurable logic structures

Look-up table structure with embedded carry logic

Gate array

Deterministic addressing of nanoscale devices assembled at sublithographic pitches

IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Semiconductor integrated circuit device

Programmable interconnect structures

Look-up table based logic macro-cells

Programmable array logic circuit employing non-volatile ferromagnetic memory cells

Programmable interconnect structures

Passgate structures for use in low-voltage applications

Mask-programmable logic macro and method for programming a logic macro

Non-volatile memory cell integrated with a latch

Apparatus and method of interconnecting nanoscale programmable logic array clusters

Method and apparatus for universal program controlled bus architecture

Customizable and Programmable Cell Array

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Look-up table structure with embedded carry logic

Look-up table based logic macro-cells

Circuit and method of controlling integrated circuit power consumption using phase change switches

Architecture and interconnect scheme for programmable logic circuits

Synchronous first-in/first-out block memory for a field programmable gate array

Variable resistance device made of a material which has an electric resistance value changing in accordance with an applied electric field and maintains the electric resistance value after being changed in a nonvolatile manner, and a semiconductor apparatus including the same

Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control

PLD architecture for flexible placement of IP function blocks

Customizable and programmable cell array

Enhanced passgate structures for reducing leakage current

Service programmable logic arrays with low tunnel barrier interpoly insulators

Integrated circuit output driver circuitry with programmable preemphasis

Combination field programmable gate array allowing dynamic reprogrammability

Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown

Programmable interconnect structures

Programmable array logic circuit employing non-volatile ferromagnetic memory cells

Look-up table based logic macro-cells

Reconfigurable circuit with a limitation on connection and method of determining functions of logic circuits in the reconfigurable circuit

Integrated logic circuit and hierarchical design method thereof

Field programmable gate array incorporating dedicated memory stacks

Device and data processing method employing the device

Control circuit and reconfigurable logic block

Programmable interconnect structures

Method and apparatus for network with multilayer metalization

Semiconductor device

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Synchronous first-in/first-out block memory for a field programmable gate array

Customizable and programmable cell array

Nanoscale wire-based sublithographic programmable logic arrays

Customizable and programmable cell array

Array of programmable cells with customized interconnections