221966 ⎘
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form; Structural details for adapting physical parameters for operating speed
Ultra low latency pattern matching system and method
#2ATTESTATION LOGIC ON MEMORY FOR MEMORY DIE VERIFICATION
#3METHOD FOR PROGRAMMING AN FPGA
#4Circuit systems and methods for reducing power supply voltage droop
#5Comparator
#6Systems and methods for routing data across regions of an integrated circuit
#7Systems and methods for routing data across regions of an integrated circuit
#8INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS
#9Generating a unique die identifier for an electronic chip
#10Scalable integrated MOSFET (SIM)
#11Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit
#12COMMUNICATION APPARATUS, SEMICONDUCTOR DEVICE, AND FREQUENCY CHARACTERISTIC CHANGING METHOD
#13Semiconductor device, electronic component, and electronic device
#14SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
#15Field programmable gate array and communication method
#16Programmable logic device and semiconductor device
#17Semiconductor device and electronic device
#18Look-up table architecture
#19Apparatus and method for correcting output signal of FPGA-based memory test device
#20Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated circuit
#21Bypassable clocked storage circuitry for dynamic voltage-frequency scaling
#22Apparatus for automatically configured interface and associated methods
#23Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated citcuit
#24Programmable LSI
#25Apparatus for improving performance of field programmable gate arrays and associated methods
#26Semiconductor device
#27Memory elements with elevated control signal levels for integrated circuits
#28Apparatus and methods for adjusting performance of programmable logic devices
#29Electronic device for a reconfigurable logic circuit
#30Power regulator circuitry for programmable logic device memory elements
#31Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
#32Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
#33Programmable logic block of FPGA using phase-change memory device
#34Interconnection and input/output resources for programmable logic integrated circuit devices
#35Efficient delay elements
#36Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
#37Level-restoring buffers for programmable interconnect circuits and method for building the same
#38Power regulator circuitry for programmable logic device memory elements
#39Apparatus and method for a programmable logic device having improved look up tables
#40FPGA ARCHITECTURE WITH THRESHOLD VOLTAGE COMPENSATION AND REDUCED LEAKAGE
#41Low static current drain logic circuit
#42Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
#43Interconnection and input/output resources for programmable logic integrated circuit devices
#44Programmable semiconductor device
#45Apparatus and methods for adjusting performance of programmable logic devices
#46High-performance static programmable logic array
#47Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
#48Interconnection resources for programmable logic integrated circuit devices
#49Interconnection and input/output resources for programmable logic integrated circuit devices
#50Fast processing path using field programmable gate array logic units
#51Re-configurable circuit and configuration switching method
#52Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
#53APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE CHARACTERISTICS OF CIRCUITRY IN PROGRAMMABLE LOGIC DEVICES
#54Configuration memory structure
#55Apparatus and methods for adjusting performance characteristics of programmable logic devices
#56Floor plan for scalable multiple level tab oriented interconnect architecture
#57Output reporting techniques for hard intellectual property blocks
#58Enhanced passgate structures for reducing leakage current
#59Differential clocking scheme in an integrated circuit having digital multiplexers
#60Routing architecture with high speed I/O bypass path
#61Interconnection resources for programmable logic integrated circuit devices
#62FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
#63FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
#64Systems and methods for routing data across regions of an integrated circuit
#65Multi-buffered shift register input matrix to FPGA
#66Generating delay values for different contexts of a circuit