221500 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse; Layout of the delay element using FET's using differential stages
GATED TRI-STATE INVERTER, AND METHOD OF OPERATING SAME
#2GATED TRI-STATE INVERTER, AND METHOD OF OPERATING SAME
#3Delay adjustment circuits
#4Delay adjustment circuits
#5Multiple adjacent slicewise layout of voltage-controlled oscillator
#6Gated tri-state inverter, and low power reduced area phase interpolator system including same, and method of operating same
#7Dynamic comparator
#8Gated tri-state inverter, and low power reduced area phase interpolator system including same, and method of operating same
#9Multiple adjacent slicewise layout of voltage-controlled oscillator
#10Oscillator device
#11Multiple adjacent slicewise layout of voltage-controlled oscillator
#12Variable delay element
#13Resonant clock amplifier with a digitally tunable delay
#14Resonant clock amplifier with a digitally tunable delay
#15Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
#16DLL circuit
#17Delay cell and phase locked loop using the same
#18Circuit including current-mode logic driver with multi-rate programmable pre-emphasis delay element
#19Delay circuit and voltage controlled oscillation circuit
#20Multiphase clock generation circuit
#21Broad-band active delay line
#22Low voltage oscillator for medical devices
#23Variable-length digitally-controlled delay chain with interpolation-based tuning
#24Delay-locked loop circuit controlled by column strobe write latency
#25DLL circuit
#26Semiconductor integrated circuit
#27Timing generator and semiconductor test apparatus
#28Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
#29Variable-length digitally-controlled delay chain with interpolation-based tuning
#30Bias circuit to stabilize oscillation in ring oscillator, oscillator, and method to stabilize oscillation in ring oscillator
#31Semiconductor device having input circuit with output path control unit
#32Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
#33Clock synchronization circuit and operation method thereof
#34Apparatus, system, and method for bitwise deskewing
#35Phased locked loop circuit including voltage controlled ring oscillator
#36Delay control circuit and delay control method
#37SEMICONDUCTOR DEVICE
#38Output buffer circuit
#39Clock generating apparatus
#40METHOD AND APPARATUS OF A RING OSCILLATOR FOR PHASE LOCKED LOOP (PLL)
#41Quadrature-phase voltage controlled oscillator
#42Duty cycle correcting circuit
#43Delay cell and phase locked loop using the same
#44CML delay cell with linear rail-to-rail tuning range and constant output swing
#45Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays
#46Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path
#47Flexible multimode logic element for use in a configurable mixed-logic signal distribution path
#48Voltage controlled oscillator
#49CML delay cell with linear rail-to-rail tuning range and constant output swing
#50Variable frequency oscillator and communication circuit with it
#51Bandpass filter circuit, band-elimination filter circuit, infrared signal processing circuit
#52Delay stage, ring oscillator, PLL-circuit and method
#53Current device and method for phase-locked loop
#54Differential ring oscillator
#55INTEGRATED CMOS CIRCUIT WITH DIFFERENTIAL OPEN DRAIN OUTPUT DRIVER
#56Hybrid current-starved phase-interpolation circuit for voltage-controlled devices
#57Partial cascode delay locked loop architecture
#58Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator
#59Differential-to-single-ended converter and phase-locked loop circuit having the same
#60DELAY UNIT OF VOLTAGE CONTROL OSCILLATOR
#61Voltage controlled oscillator
#62Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
#63PLL with controlled VCO bias
#64Voltage controlled oscillator with duty correction
#65Partial cascode phase locked loop architecture
#66Delay cell for voltage controlled oscillator including delay cells connected as a ring oscillator
#67Delay circuit
#68Voltage controlled oscillator and delay circuit thereof
#69Delay locked loop circuitry for clock delay adjustment
#70Oscillator delay stage with active inductor
#71Frequency-controlled DLL bias
#72Differential type delay cells and methods of operating the same
#73Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device
#74Integrated circuit systems and devices having high precision digital delay lines therein
#75Generating an oscillating signal according to a control current
#76High speed amplifier incorporating pre-emphasis
#77High noise rejection voltage-controlled ring oscillator architecture
#78Programmable jitter generator
#79Method and circuitry for reducing duty cycle distortion in differential delay lines
#80Synchronous data serialization circuit