221551 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices
DYNAMIC LATCH, DYNAMIC D FLIP-FLOP, DATA OPERATION UNIT, CHIP, HASH BOARD, AND COMPUTING DEVICE
#2SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE
#3APPARATUS AND METHOD FOR MONITORING DUTY CYCLE OF MEMORY CLOCK SIGNAL
#4Low-latency time-to-digital converter with reduced quantization step
#5Timing sequence generation circuit
#6Clock data recovery circuit of display and clock recovery circuit thereof
#7Semiconductor device, display module, and electronic device
#8Memory device for correcting pulse duty and memory system including the same
#9Clock spread spectrum circuit, electronic equipment, and clock spread spectrum method
#10Self-correcting modular-redundancy-memory device
#11Circuit having a plurality of modes
#12SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE
#13Phase error correction for clock signals
#14Semiconductor device, display module, and electronic device
#15Techniques based on electromigration characteristics of cell interconnect
#16Circuit for meeting setup and hold times of a control signal with respect to a clock
#17Clock generator for multi-channel analog to digital converter
#18Circuit and method for reducing mismatch for combined clock signal
#19Memory device including delay circuit having gate insulation films with thicknesses different from each other
#20Method and apparatus for phase-aligned 2X frequency clock generation
#21Multi-stage frequency dividers and poly-phase signal generators
#22Power efficient high speed latch circuits and systems
#23Electronic circuit, solid state image capturing apparatus and method of controlling electronic circuit
#24Electronic latch circuit and a generic multi-phase signal generator
#25Skew adjustment circuit, semiconductor device, and skew calibration method
#26Encoding circuit, ad conversion circuit, imaging device, and imaging system including a delay circuits having opposite polarity output terminals
#27Techniques based on electromigration characteristics of cell interconnect
#28Memory device including delay circuit having gate insulation films with thicknesses different from each other
#29Circuit for generating at least two rectangular signals with adjustable phase shift and use of said circuit
#30Bandwidth amplification using pre-clocking
#31Data transmitter, data receiver and smart device using the same
#32Semiconductor device and method of controlling semiconductor device
#33Semiconductor device, display module, and electronic device
#34Clock control circuit, receiver, and communication device
#35Multi-phase clock generation circuit
#36Multi-phase clock generator and data transmission lines
#37Apparatus for generating a plurality of signals
#38Phase shift generating circuit
#39Phase delay line
#40Semiconductor device
#41QUARTER CYCLE DELAY CLOCK GENERATOR
#42Clock circuitry
#43Delay circuit and semiconductor device
#44Delay circuit and semiconductor device
#45Clock generator circuit, signal multiplexing circuit, optical transmitter, and clock generation method
#46Multiphase clock generator circuit
#47Open-loop digital duty cycle correction circuit without DLL
#48Selectively providing clock signals using a programmable control circuit
#49Analog front end circuit of an optical pulse energy digitizer