221550 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
Sub-classes:CLOCK CONTROL CIRCUIT, MEMORY, AND CLOCK CONTROL METHOD
#2METHOD AND STANDARD MODULE FOR AMPLIFYING PULSED POWER
#3LOW-JITTER RANDOM CLOCK GENERATION CIRCUIT
#4CLOCK TRANSMISSION CIRCUIT, IMAGING ELEMENT, AND METHOD FOR MANUFACTURING CLOCK TRANSMISSION CIRCUIT
#5MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
#6Clock signal delay path unit and semiconductor memory device including the same
#7TIME-DELAY CIRCUIT FOR A DIGITAL SIGNAL, PARTICULARLY FOR A CLOCK SIGNAL
#8Apparatus and methods for providing voltages to conductive lines between which clock signal lines are disposed
#9Adaptive oscillator for clock generation
#10Apparatuses and methods for providing clock signals in a semiconductor device
#11Compensated comparator
#12Method and apparatus for clock signal distribution
#13SINGLE CLOCK SOURCE FOR A MULTIPLE DIE PACKAGE
#14Unipolar logic circuits
#15SEMICONDUCTOR DEVICE
#16Adaptive oscillator for clock generation
#17Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry
#18Clock generating circuit and semiconductor apparatus including the same
#19Phase detection circuit
#20Phase interpolators and push-pull buffers
#21Switch control circuit
#22Semiconductor device
#23Circuitry useful for clock generation and distribution
#24MULTIPHASE OSCILLATING SIGNAL GENERATION AND ACCURATE FAST FREQUENCY ESTIMATION
#25DATA DRIVER, DISPLAY PANEL DRIVING DEVICE, AND DISPLAY DEVICE
#26Circuitry useful for clock generation and distribution
#27Phase interpolators and push-pull buffers
#28Pulse generator and method for generating pulse
#29Semiconductor device having DLL circuit
#30SEMICONDUCTOR INTEGRATED CIRCUIT
#31Delay circuit and method for delaying signal
#32Clock frequency divider circuit, clock distribution circuit, clock frequency division method, and clock distribution method
#33Clock frequency divider circuit and clock frequency division method
#34Clock buffer circuit
#35Reducing power-supply-induced jitter in a clock-distribution circuit
#36Multi-phase clock signal generating circuit having improved phase difference and a controlling method thereof
#37Method and apparatus for adaptive clock phase control for LSI power reduction
#38Semiconductor integrated circuit
#39System for generating a multiple phase clock
#40Fraction-N frequency divider and method thereof
#41Delay circuit and semiconductor device
#42Circuit for distributing an initial signal with a tree structure, protected against logic random events
#43System and method for multiple-phase clock generation
#44Fan out buffer and method therefor
#45Delay circuit and semiconductor device
#46Level shift circuit
#47Clock distribution network using feedback for skew compensation and jitter filtering
#48Delay circuit and control method of the delay circuit
#49Adaptive body bias for clock skew compensation
#50Semiconductor integrated circuit and manufacturing method
#51Programmable jitter signal generator
#52Method for multiple-phase splitting by phase interpolation and circuit the same
#53Method and standard module for amplifying pulsed power
#54Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed
#55Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry