221553 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of delay lines
Pipeline clock driving circuit, computing chip, hashboard, and computing device
#2MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
#3Clock signal delay path unit and semiconductor memory device including the same
#4Image sensor with delay line charge pump voltage generator
#5Bi-directional interface for device feedback
#6Adaptive oscillator for clock generation
#7High speed data synchronization
#8VDS comparator rise P, fall P, on late, off late outputs for ZVC timing
#9Increasing resolution of on-chip timing uncertainty measurements
#10High-resolution FET VDS zero-volt-crossing timing detection scheme in a wireless power transfer system
#11Adaptive oscillator for clock generation
#12Clock recovery circuit, semiconductor integrated circuit device, and radio frequency tag
#13Phase control of clock signal based on feedback
#14Multi-channel clock distribution circuit and electronic device
#15Delay line with short recovery time
#16Method for synchronously distributing a digital signal over N identical adjacent blocks of an integrated circuit
#17Oscillation circuit, voltage controlled oscillator, and serial data receiver
#18Multi-phase clock signal generation circuits
#19Semiconductor device, a method of improving a distortion of an output waveform, and an electronic apparatus
#20Systems and methods for providing a clock signal
#21Image sensor and a configuration for improved skew time
#22Ring oscillator
#23Delay circuit
#24Systems and methods for providing a clock signal
#25Phase shift circuit with lower intrinsic delay
#26Apparatus and method for multi-phase clock generation
#27Phase shift circuit with lower intrinsic delay
#28Systems and methods for providing a clock signal
#29Method and apparatus for data transfer using a time division multiple frequency scheme supplemented with polarity modulation
#30Data transfer using frequency notching of radio-frequency signals
#31Information processing apparatus with adjustable system clock
#32Method and apparatus for data transfer using wideband bursts
#33Information processing apparatus with adjustable system clock
#34Geometric remapping with delay lines
#35Clock signal distribution network and method
#36Clock skew calibration for time interleaved ADCS
#37Method and system for controller hold-margin of semiconductor memory device
#38Distributed voltage and temperature compensation for clock deskewing
#39Distributed multi-phase clock generator having coupled delay-locked loops