Robert E. Palmer

SYMMETRIC I/O PORTS

CONFIGURABLE ELECTRICAL PAD DIE PACKAGE

QUAD-CHANNEL MEMORY MODULE WITH INTERLEAVED DATA COMMUNICATION

MEMORY WITH DATA LOOP-BACK

Maintenance Operations in a DRAM

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

Maintenance operations in a DRAM

Signal receiver with skew-tolerant strobe gating

Low-power multi-domain synchronizer

Maintenance operations in a DRAM

Integrated transmitter slew rate calibration

Adaptive equalization using correlation of data patterns with errors

Memory IC with data loopback

Adaptive equalization using correlation of data patterns with errors

Maintenance operations in a DRAM

Adaptive equalization correlating data patterns with transition timing

Clock-forwarding memory controller with mesochronously-clocked signaling interface

Maintenance operations in a DRAM

Adaptive equalization using correlation of data patterns with errors

Maintenance operations in a DRAM

Maintenance operations in a DRAM

Adaptive equalization using correlation of data patterns with errors

Signaling interface with phase and framing calibration

Memory controller with dynamic core-transfer latency

Maintenance operations in a DRAM

Maintenance operations in a DRAM

Chip-to-chip signaling link timing calibration

Maintenance operations in a DRAM

Memory controller with transaction-queue-dependent power modes

Read strobe gating mechanism

In-situ delay element calibration

Memory controller with transaction-queue-monitoring power mode circuitry