Rambus Inc.

Dynamically changing data access bandwidth by selectively enabling and disabling data links

Clocking architecture supporting multiple data rates and reference edge selection

Stall-driven multi-processing

Wireline link with crosstalk reduction based on controlled channel delay

Power Efficient Circuits and Methods for Phase Alignment

PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER

MEMORY DEVICE WITH STAGGERED ACCESS

DETERMINISTIC OPERATION OF STORAGE CLASS MEMORY

CLOCK BUFFER

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

MEMORY SYSTEM FOR FLEXIBLY ALLOCATING COMPRESSED STORAGE

Split-path equalizer and related methods, devices and systems

TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS

PHYSICALLY UNCLONEABLE FUNCTION AS SECURE STORAGE

On-die termination of address and command signals

LOW OVERHEAD REFRESH MANAGEMENT OF A MEMORY DEVICE

INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY

BLOCK COPY

STORAGE AND ACCESS OF DATA AND TAGS IN A MULTI-WAY SET ASSOCIATIVE CACHE

HIGH PERFORMANCE PERSISTENT MEMORY

HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE

HYBRID MEMORY

SERIAL PRESENCE DETECT LOGGING

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

Energy-Efficient Error-Correction-Detection Storage

MEMORY DEVICE HAVING NON-UNIFORM REFRESH

Memory component with programmable data-to-clock ratio

INTERFACE CLOCK MANAGEMENT

MEMORY CONTROLLER PARTITIONING FOR HYBRID MEMORY SYSTEM

Memory controller operable in data loop-back mode

BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE

Signal skew in source-synchronous system

MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATES

MEMORY MODULE WITH DOUBLE DATA RATE COMMAND AND DATA INTERFACES SUPPORTING TWO-CHANNEL AND FOUR-CHANNEL MODES

DATA TRANSMISSION USING DELAYED TIMING SIGNALS

CONFIGURABLE IN-ARRAY EVENT TRACKING

High capacity, high performance memory system

DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE

Energy efficient storage of error-correction-detection information

Multi-Modal Refresh of Dynamic, Random-Access Memory

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

SERIAL PRESENCE DETECT RELIABILITY

MEMORY MODULE WITH PERSISTENT CALIBRATION

LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH DEDICATED READ-WRITE DATA PATHS

OPTIMIZING POWER IN A MEMORY DEVICE

Memory system using asymmetric source-synchronous clocking

DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES

Reordering memory controller

Memory access during memory calibration

Memory module register access

Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture

Maintenance operations in a DRAM

LOAD-REDUCED DRAM STACK

Memory error detection

MEMORY DEVICE HAVING HIDDEN REFRESH

Memory component with input/output data rate alignment

Multi-Element Memory Device with Power for Individual Elements

BURST-TOLERANT DECISION FEEDBACK EQUALIZATION

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH INTERVALS

Load reduced memory module

ADDRESS MAPPING FOR IMPROVED RELIABILITY

Unsuccessful write retry buffer

Methods and apparatuses for addressing memory caches

Memory device and repair method with column-based error code tracking

Area-efficient, width-adjustable signaling interface

Interface with Variable Data Rate

MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES

DATA BUFFER FOR MEMORY DEVICES WITH UNIDIRECTIONAL PORTS

DC-DC CONVERTER WITH SWITCHING NOISE SUPPRESSION CIRCUITRY

Protocol for refresh between a memory controller and a memory device

Stacked DRAM device and method of manufacture

Error coalescing

STACKED DEVICE COMMUNICATION

MEMORY SYSTEM WITH ACTIVATE-LEVELING METHOD

ASYNCHRONOUS ARBITRATION ACROSS CLOCK DOMAINS FOR REGISTER WRITES IN AN INTEGRATED CIRCUIT CHIP

High level instructions with lower-level assembly code style primitives within a memory appliance for accessing memory

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

High-Performance, High-Capacity Memory Modules and Systems

Structure for delivering power

INTEGRATED CIRCUIT MEMORY DEVICES WITH UNIDIRECTIONAL PORTS FOR CONCURRENT INTERFACE OPERATIONS

QUAD-CHANNEL MEMORY MODULE

STACKED SEMICONDUCTOR DEVICE

Boosted writeback voltage

DEVICE MANAGEMENT SYSTEM WITH EMBEDDED MANAGEMENT OPERATION DATABASE

LOW OVERHEAD PAGE RECOMPRESSION

BUFFER DEVICE WITH LOW-LATENCY SKID MODE FOR DATA FRESHNESS

HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE

Forwarding signal supply voltage in data transmission system

Remedial action indication

Dynamically changing data access bandwidth by selectively enabling and disabling data links

CLOCK AND MULTI-VALUED DATA SIGNALLING

DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH VARIABLE BURST LENGTHS

Memory controller with staggered request signal output

PARTIAL ARRAY REFRESH TIMING

Phase-Based Lock Detector with Programmable Frequency Offset Tolerance

Circuits and methods for self-adaptive decision-feedback equalization in a memory system