Inventor profile of:

Philip Ng

City:

Toronto

Country:

Canada

Published Applications:

31

Last publication date:

2026-04-02

Top Assignees for applications by Philip Ng

The entities that hold a legal rights for patent applications filed by inventor Ng Philip:

Recent patent applications by Ng Philip

Philip Ng from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-02
US20260093623A1
Physics

MULTI-HOST REMOTE MEMORY ACCESS

#2 | 2024-08-29
US20240289151A1
Physics

ADDRESS-SPACE-IDENTIFIER-BASED SECURITY OF DATA TRANSFER REQUESTS

#3 | 2024-08-29
US20240289150A1
Physics

SECURE MANAGEMENT OF DEVICE CONTROL INFORMATION IN CONFIDENTIAL COMPUTING ENVIRONMENTS

#4 | 2024-07-04
US20240220429A1
Physics

SECURE DIRECT MEMORY ACCESS

#5 | 2024-07-04
US20240220417A1
Physics

SEGMENTED NON-CONTIGUOUS REVERSE MAP TABLE

#6 | 2024-07-04
US20240220297A1
Physics

INTERRUPT CONTROL USING A GUEST OWNED BACKING PAGE

#7 | 2024-07-04
US20240220296A1
Physics

SECURE MEMORY-MAPPED INPUT/OUTPUT

#8 | 2024-06-27
US20240211300A1
Physics

Interrupt cache configuration

#9 | 2024-06-20
US20240202015A1
Physics

Accessing Multiple Physical Partitions of a Hardware Device

#10 | 2023-11-23
US20230376438A1
Physics

Address Translation Services Buffer

#11 | 2023-08-03
US20230244623A1
Physics

Arbitration allocating requests during backpressure

#12 | 2022-10-06
US20220318040A1
Physics

System and method for providing page migration

#13 | 2022-09-29
US20220308756A1
Physics

Performing Memory Accesses for Input-Output Devices using Encryption Keys Associated with Owners of Pages of Memory

#14 | 2022-09-29
US20220308755A1
Physics

Handling the migration of pages of memory accessible by input-output devices

#15 | 2022-08-25
US20220269621A1
Physics

Providing copies of input-output memory management unit registers to guest operating systems

#16 | 2022-06-30
US20220206976A1
Physics

Address translation services buffer

#17 | 2022-06-30
US20220206942A1
Physics

Method, system, and apparatus for supporting multiple address spaces to facilitate data movement

#18 | 2022-06-30
US20220206700A1
Physics

Migrating pages of memory accessible by input-output devices

#19 | 2021-03-25
US20210089480A1
Physics

Providing interrupts from an input-output memory management unit to guest operating systems

#20 | 2020-12-10
US20200387326A1
Physics

Guest operating system buffer and log accesses by an input-output memory management unit

#21 | 2020-12-03
US20200379927A1
Physics

Providing copies of input-output memory management unit registers to guest operating systems

#22 | 2020-10-22
US20200334058A1
Physics

Domain identifier and device identifier translation by an input-output memory management unit

#23 | 2020-07-16
US20200226081A1
Physics

Light-weight memory expansion in a coherent memory system

#24 | 2020-06-18
US20200192842A1
Physics

MEMORY REQUEST CHAINING ON BUS

#25 | 2020-06-04
US20200176071A1
Physics

Memory initialization reporting and control

#26 | 2019-08-29
US20190265774A1
Physics

Aligning active and idle phases in a mixed workload computing platform

#27 | 2018-08-16
US20180232320A1
Physics

Controlling access by IO devices to pages in a memory in a computing device

#28 | 2015-04-30
US20150120978A1
Physics

Input/output memory map unit and northbridge

#29 | 2015-04-16
US20150106916A1
Physics

Leveraging a peripheral device to execute a machine instruction

#30 | 2012-09-27
US20120246381A1
Physics

Input Output Memory Management Unit (IOMMU) Two-Layer Addressing

#31 | 2012-06-21
US20120159039A1
Physics

Generalized control registers

InventorID:

1132373 ⎘