Bomy Chen

Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

Self Limiting Method For Programming A Non-volatile Memory Cell To One Of A Plurality Of MLC Levels

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE

Storage element for controlling a logic circuit, and a logic device having an array of such storage elements

Array of contactless non-volatile memory cells

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing

Method of trimming semiconductor elements with electrical resistance feedback

Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Novel chalcogenide material, switching device and array of non-volatile memory cells

NOR flash memory

Method of making phase change memory device employing thermally insulating voids and sloped trench

Single gate-non-volatile flash memory cell

Word line voltage boosting circuit and a memory array incorporating same

Bi-directional read/program non-volatile floating gate memory array, and method of formation

Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation

Method of manufacturing an isolation-less, contact-less array of bi-directional read/program non-volatile floating gate memory cells with independent controllable control gates

Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region

Method of making a bi-directional read/program non-volatile floating gate memory cell

Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same

Dynamically tunable resistor or capacitor using a non-volatile floating gate memory cell

Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements

Method of trimming semiconductor elements with electrical resistance feedback

Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same

Stacked gate memory cell with erase to gate, array, and method of manufacturing

Method for reading an array of multi-bit ROM cells with each cell having bi-directional read

NROM device

Non-destructive read ferroelectric memory cell, array and integrated circuit device

Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same

Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation

Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby

Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array

Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing

Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region

Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation

Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation

Memory device and method of operating same

Stacked gate memory cell with erase to gate, array, and method of manufacturing

Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region

Memory device with discrete layers of phase change memory material

Semiconductor memory array of floating gate memory cells with buried floating gate

Method of manufacturing an array of bi-directional nonvolatile memory cells

Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells

Multi-bit ROM cell with bi-directional read and a method for making thereof

Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array

Phase change memory device employing thermal-electrical contacts with narrowing electrical current paths

Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing