Silicon Storage Technology, Inc.

COARSE AND FINE PROGRAMMING OF NON-VOLATILE MEMORY CELLS

ACCELERATED PROGRAMMING OF FOUR GATE, SPLIT-GATE FLASH MEMORY CELLS

PROGRAM SPEED COMPENSATION FOR NON-VOLATILE MEMORY CELLS

SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER TO GENERATE DIGITAL OUTPUT FROM VECTOR-BY-MATRIX MULTIPLICATION ARRAY

SYSTEM AND METHOD FOR IMPLEMENTING TEMPERATURE COMPENSATION IN A MEMORY DEVICE

Memory Device Formed On Silicon-On-Insulator Substrate, And Method Of Making Same

ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM

Neural network classifier using array of three-gate non-volatile memory cells

OUTPUT BLOCK FOR ARRAY OF NON-VOLATILE MEMORY CELLS

NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLS

Neural network classifier using array of three-gate non-volatile memory cells

Pumping controller for a plurality of charge pump units

CURRENT-TO-VOLTAGE CONVERTER COMPRISING COMMON MODE CIRCUIT

Memory cell array with row direction gap between erase gate lines and dummy floating gates

ARRAY OF NON-VOLATILE MEMORY CELLS TO STORE DATA IN ANALOG FORM AND DIGITAL FORM

DUAL-PATH CHARGE PUMP

Grouping and error correction for non-volatile memory cells

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Multiple row programming operation in artificial neural network array

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Input and output blocks for an array of memory cells

Output circuit

Neural network device

Neural network array comprising one or more coarse cells and one or more fine cells

DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS IN A NEURAL NETWORK

DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS

Method of screening non-volatile memory cells

VECTOR-BY-MATRIX-MULTIPLICATION ARRAY UTILIZING ANALOG OUTPUTS

CALIBRATION OF ELECTRICAL PARAMETERS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate

METHOD OF FORMING A DEVICE WITH PLANAR SPLIT GATE NON-VOLATILE MEMORY CELLS, PLANAR HV DEVICES, AND FINFET LOGIC DEVICES ON A SUBSTRATE

Setting levels for a programming operation in a neural network array

Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area

MEMORY DEVICE OF NON-VOLATILE MEMORY CELLS

Method Of Scanning An Image Using Non-volatile Memory Array Neural Network Classifier

ARTIFICIAL NEURAL NETWORK COMPRISING AN ANALOG ARRAY AND A DIGITAL ARRAY

Summing circuit for neural network

Output circuitry for non-volatile memory array in neural network

Neural network classifier using array of three-gate non-volatile memory cells

Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation

SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME

Neural memory array storing synapsis weights in differential cell pairs

Hierarchical ROM encoder system for performing address fault detection in a memory system

Determination of a bias voltage to apply to one or more memory cells in a neural network

Transceiver for providing high voltages for erase or program operations in a non-volatile memory system

ADJUSTABLE PROGRAMMING CIRCUIT FOR NEURAL NETWORK

Method of determining defective die containing non-volatile memory cells

Hybrid memory system configurable to store neural memory weight data in analog form or digital form

INPUT CIRCUITRY FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Input function circuit block and output neuron circuit block coupled to a vector-by-matrix multiplication array in an artificial neural network

Read and programming decoding system for analog neural memory

Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network

Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells

Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise

Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network

Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network

Precise data tuning method and apparatus for analog neural memory in an artificial neural network

SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

OUTPUT CIRCUIT FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

ULTRA-PRECISE TUNING OF NEURAL MEMORY CELLS

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Virtual ground non-volatile memory array

Testing of analog neural memory cells in an artificial neural network

Compensation for leakage in an array of analog neural memory cells in an artificial neural network

Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same

Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate

Programming analog neural memory cells in deep learning artificial neural network

Method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices

Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates

Architectures for storing and retrieving system data in a non-volatile memory system

Word line and control gate line tandem decoder for analog neural memory in deep learning artificial neural network

Deep learning neural network classifier using non-volatile memory array

Wear leveling in EEPROM emulator formed of flash memory cells

Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same

Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same

Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices

Concurrent write and verify operations in an analog neural memory

Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks

Method of forming split gate memory cells with thinner tunnel oxide

Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network

Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise

Neural network classifier using array of three-gate non-volatile memory cells

Method of forming split gate memory cells with thinned side edge tunnel oxide

Method of making memory cells, high voltage devices and logic devices on a substrate

Word line and control gate line tandem decoder for analog neural memory in deep learning artificial neural network

Self-timed sensing architecture for a non-volatile memory system

Analog neural memory array in artificial neural network comprising logical cells and improved programming mechanism

Analog neural memory array in artificial neural network with source line pulldown mechanism

Decoders for analog neural memory in deep learning artificial neural network

Programmable output blocks for analog neural memory in a deep learning artificial neural network

Non-volatile memory system using strap cells in source line pull down circuits

FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling

Precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network

Output circuitry for non-volatile memory array in neural network

Analog neural memory array storing synapsis weights in differential cell pairs in artificial neural network

Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power

Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices

Wear leveling in EEPROM emulator formed of flash memory cells